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US20120094465 INTEGRATED PLANAR AND MULTIPLE GATE FETS  
A multiple gate field effect transistor and a planar field effect transistor formed in the same substrate each have a top planar surface underneath each corresponding gate that are co-planar with...
US20130307033 Borderless Contact For An Aluminum-Containing Gate  
An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement...
US20130071977 METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS  
Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy...
US20130168780 METHOD AND STRUCTURE TO REDUCE FET THRESHOLD VOLTAGE SHIFT DUE TO OXYGEN DIFFUSION  
Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work...
US20060270183 Isolation structure and method of forming the same  
An isolation structure may include a trench formed on a surface of a substrate. A first isolation pattern may be provided on an inner face of the trench to define an auxiliary trench. A second...
US20100015776 Shallow Trench Isolation Corner Rounding  
A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion...
US20120126374 Forming Three Dimensional Isolation Structures  
A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first...
US20140220759 METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS  
Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having...
US20110254118 Schottky Diode with Control Gate for Optimization of the On State Resistance, the Reverse Leakage, and the Reverse Breakdown  
A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that...
US20120223407 Superior Integrity of High-K Metal Gate Stacks by Capping STI Regions  
When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the...
US20130270644 REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING  
Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further...
US20130082318 INTEGRATION OF eNVM, RMG, AND HKMG MODULES  
A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two...
US20130049161 NITRIDE SHALLOW TRENCH ISOLATION (STI) STRUCTURES AND METHODS FOR FORMING THE SAME  
A shallow trench isolation (STI) structure and methods for forming the same provide an STI structure with a top surface formed completely of silicon nitride. The methods for forming the STI...
US20080102598 III-Nitride wafer fabrication  
A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.
US20090317957 Method for Forming Isolation Structures  
A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart...
US20150004773 METHOD FOR FORMING SHALLOW TRENCH ISOLATION  
A method for forming shallow trench isolation (STI) structures includes using a hard mask, such as silicon nitride, in shallow trench etching and also as a polishing stop layer in planarizing the...
US20070172965 NON-DESTRUCTIVE TRENCH VOLUME DETERMINATION AND TRENCH CAPACITANCE PROJECTION  
Methods of determining trench volume are disclosed. In one embodiment, the method includes providing a semiconductor substrate with at least one trench in a trench area; filling each trench with a...
US20140117507 DOUBLE TRENCH WELL FORMATION IN SRAM CELLS  
A method is provided for forming SRAM cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each...
US20080146001 Pre-STI nitride descum step for increased margin against STI seam voids  
A method of forming a shallow trench isolation structure is provided, and includes forming a mask structure over active regions of a substrate, thereby defining a trench region therebetween. A...
US20110254084 STRUCTURES AND METHODS OF FABRICATING DUAL GATE DEVICES  
First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1...
US20070178664 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF FABRICATING THE SAME  
A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP)...
US20140073109 FABRICATING METHOD OF SHALLOW TRENCH ISOLATION STRUCTURE  
A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a...
US20120171842 STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION  
A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the...
US20120276707 METHOD FOR FORMING TRENCH ISOLATION  
A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating...
US20050266654 Barrier to amorphization implant  
A method includes forming a first and a second semiconductor region which are joined at a semiconductor junction. The first and second semiconductor regions are truncated with an isolation trench,...
US20120190168 METHOD FOR FORMING TRENCHES AND TRENCH ISOLATION ON A SUBSTRATE  
A method for forming trench isolation on a substrate includes providing a substrate having thereon a pad layer and a hard mask; forming a first shallow trench in a first area and a second trench...
US20120077327 Formation of a Shallow Trench Isolation Structure  
A method of forming a shallow trench isolation structure such that the shoulders of the wall formations on either side of the trench are rounded, whilst the walls and floor of the trench as well...
US20150097245 SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS  
A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a...
US20090127626 STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION  
A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the...
US20090321834 Substrate fins with different heights  
A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.
US20130328157 SPACER ISOLATION IN DEEP TRENCH  
A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench...
US20120235245 SUPERIOR INTEGRITY OF HIGH-K METAL GATE STACKS BY REDUCING STI DIVOTS BY DEPOSITING A FILL MATERIAL AFTER STI FORMATION  
When forming sophisticated semiconductor devices on the basis of high-k metal gate electrode structures, which are to be provided in an early manufacturing stage, the encapsulation of the...
US20090191688 Shallow Trench Isolation Process Using Two Liners  
A method for making STI structure includes etching a STI trench through a nitride layer, through an oxide layer, and into a silicon layer. The method also includes forming a sacrificial liner,...
US20130109151 METHOD FOR FORMING VOID-FREE DIELECTRIC LAYER  
A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and...
US20130043535 ISOLATION REGION FABRICATION FOR REPLACEMENT GATE PROCESSING  
A method for isolation region fabrication for replacement gate integrated circuit (IC) processing includes forming a plurality of dummy gates on a substrate; forming a block mask over the...
US20070155122 TRENCH ISOLATION STRUCTURE HAVING DIFFERENT STRESS  
By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative...
US20130115751 BORON-CONTAINING HYDROGEN SILSESQUIOXANE POLYMER, INTEGRATED CIRCUIT DEVICE FORMED USING THE SAME, AND ASSOCIATED METHODS  
A composition includes a boron-containing hydrogen silsesquioxane polymer having a structure that includes: silicon-oxygen-silicon units, and oxygen-boron-oxygen linkages in which the boron is...
US20050275059 Isolation trench arrangement  
Isolation trench arrangement, which isolates adjacent semiconductor structures (1), (2), an isolation trench (3) being formed in such a way that it penetrates from a substrate surface into the...
US20130193516 SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION  
SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two...
US20050158963 Method of forming planarized shallow trench isolation  
Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments...
US20080042224 Soi Disks Comprising Mems Structures and Filled Isolating Trenches Having a Defined Cross-Section  
Forming of filled isolation trenches, in particular the transition area in trenches and recesses free of silicon during the realisation of MEMS structures of SOI wafers. A reliable dielectic...
US20120038030 METHOD FOR FILLING CAVITIES IN WAFERS, CORRESPONDINGLY FILLED BLIND HOLE AND WAFER HAVING CORRESPONDINGLY FILLED INSULATION TRENCHES  
A method is described for filling cavities in wafers, the cavities being open to a predetermined surface of the wafer, including the following steps: applying a lacquer-like filling material to...
US20070246795 Dual depth shallow trench isolation and methods to form same  
Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes...
US20140094017 MANUFACTURING METHOD FOR A SHALLOW TRENCH ISOLATION  
A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one...
US20140001596 Sinker with a Reduced Width  
The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in...
US20070155121 TECHNIQUE FOR FORMING AN ISOLATION TRENCH AS A STRESS SOURCE FOR STRAIN ENGINEERING  
By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one...
US20120178236 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION  
A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top...
US20110081765 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION  
A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top...
US20080290461 DEEP TRENCH ISOLATION FOR POWER SEMICONDUCTORS  
An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled...
US20140220760 INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS  
A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV...