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US20120196425 High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials  
When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization...
US20130143385 STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS  
Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier...
US20120223407 Superior Integrity of High-K Metal Gate Stacks by Capping STI Regions  
When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the...
US20130087880 MEMS DEVICE AND METHOD OF MANUFACTURE  
A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels,...
US20120126359 Structure to Reduce Etching Residue  
A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal...
US20120276707 METHOD FOR FORMING TRENCH ISOLATION  
A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating...
US20070042560 Method for growing thin nitride film onto substrate and thin nitride film device  
The present invention provides a method for growing a thin nitride film over a substrate and a thin nitride film device, in which the polarity of the thin nitride film can be controlled by a low...
US20090243029 METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS  
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric...
US20100029057 SILICONE RESIN COMPOSITION AND METHOD OF FORMING A TRENCH ISOLATION  
A silicone resin which is represented by the following rational formula (1) and solid at 120° C.: (H2SiO)n(HSiO1.5)m(SiO2)k (1) wherein n, m and k are each a number, with the proviso that, when ...
US20120292664 Integrated Circuit (IC) Chip Having Both Metal and Silicon Gate Field Effect Transistors (FETs) and Method of Manufacture  
Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a...
US20090189216 SEMICONDUCTOR COMPONENT INCLUDING A DRIFT ZONE AND A DRIFT CONTROL ZONE  
Semiconductor component including a drift region and a drift control region. One embodiment provides a drift zone and a drift control zone. A drift control zone dielectric is arranged between the...
US20140167206 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF MANUFACTURE  
A semiconductor device includes a substrate and a first and second plurality of stack structures arranged over the substrate. The first and second plurality of stack structures are separated by a...
US20140197467 HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE  
A JFET structure includes a first JFET having a first terminal and a second JFET neighboring with the first JFET. Both JFETs commonly share the first terminal and the first terminal is between the...
US20140167128 Memory Gate Landing Pad Made From Dummy Features  
Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at...
US20120208341 Alignment Marks for Polarized Light Lithography and Method for Use Thereof  
Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the...
US20090321870 SHUTTLE WAFER AND METHOD OF FABRICATING THE SAME  
A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the...
US20140001595 Layout Architecture for Performance Improvement  
An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a...
US20120126336 Isolation FET for Integrated Circuit  
An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the...
US20080237573 Mechanism for forming a remote delta doping layer of a quantum well structure  
A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
US20090209081 Silicon Dioxide Thin Films by ALD  
Methods are provided for depositing silicon dioxide containing thin films on a substrate by atomic layer deposition ALD. By using disilane compounds as the silicon source, good deposition rates and...
US20100025726 Lateral Devices Containing Permanent Charge  
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges...
US20120190167 MECHANISMS OF DOPING OXIDE FOR FORMING SHALLOW TRENCH ISOLATION  
The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such...
US20090298246 TECHNIQUES FOR FABRICATING A NON-PLANAR TRANSISTOR  
Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may...
US20080283925 Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement  
In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of...
US20120074496 Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same  
Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing...
US20110250731 PREFERENTIAL DIELECTRIC GAPFILL  
Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric...
US20080026540 Integration for buried epitaxial stressor  
Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a...
US20070107655 Sub-resolutional laser annealing mask  
A mask with sub-resolution aperture features and a method for smoothing an annealed surface using a sub-resolution mask pattern are provided. The method comprises: supplying a laser beam having a...
US20110177669 METHOD OF CONTROLLING TRENCH MICROLOADING USING PLASMA PULSING  
Methods and apparatus for controlling microloading, such as within cell microloading between adjacent cells or isolated/dense microloading between areas of isolated or dense features during shallow...
US20070243692 Methods of filling isolation trenches for semiconductor devices and resulting structures  
The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped...
US20090079005 Integrated Circuits and Methods of Design and Manufacture Thereof  
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of...
US20120319230 ETCHING NARROW, TALL DIELECTRIC ISOLATION STRUCTURES FROM A DIELECTRIC LAYER  
Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor...
US20070210403 Isolation regions and their formation  
A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to...
US20090001503 SEMICONDUCTOR DEVICE HAVING FLOATING BODY ELEMENT AND BULK BODY ELEMENT AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body...
US20130187196 Integrated Circuit Including Field Effect Transistor Structures with Gate and Field Electrodes and Methods for Manufacturing and Operating an Integrated Circuit  
An integrated circuit includes a first and a second field effect transistor structure. The first field effect transistor structure includes a first gate electrode structure and a first field...
US20060228864 Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using Epi-Si growth process  
A semiconductor device having a transistor and a storage capacitor. The transistor includes source and drain regions formed on a substrate. The storage capacitor is coupled to the transistor. The...
US20090166810 Semiconductor Device Crack-Deflecting Structure and Method  
The invention relates to microelectronic semiconductor devices, and to mass-production of the same on semiconductor wafers with novel crack-deflecting structures and methods. According to the...
US20130171802 FULL WAFER PROCESSING BY MULTIPLE PASSES THROUGH A COMBINATORIAL REACTOR  
Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are...
US20130164906 FULL WAFER PROCESSING BY MULTIPLE PASSES THROUGH A COMBINATORIAL REACTOR  
Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are...
US20130154051 METHOD FOR FORMING A DEEP TRENCH IN A MICROELECTRONIC COMPONENT SUBSTRATE  
A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The...
US20080017949 Front-rear contacts of electronics devices with induced defects to increase conductivity thereof  
An electronic device is proposed. The device is integrated in a chip including at least one stacked layer having a front surface and a rear surface opposite the front surface, the device including:...
US20120083093 ISOLATION STRUCTURE FOR A MEMORY CELL USING AL2O3 DIELECTRIC  
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated...
US20090072341 BURIED LOW-RESISTANCE METAL WORD LINES FOR CROSS-POINT VARIABLE-RESISTANCE MATERIAL MEMORIES  
Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode....
US20090315114 STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS  
Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier...
US20140225186 LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED AIRGAP FIELD PLATES  
Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having tapered dielectric field plates positioned laterally between conductive...
US20100090278 High-Voltage Transistor with High Current Load Capacity and Method for its Production  
An isolation area (10) is provided over a drift region (12) with a spacing (d) to a contact area (4) provided for a drain connection (D). The isolation area is used as an implantation mask, in...
US20140070358 METHOD OF TAILORING SILICON TRENCH PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR  
A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor...
US20130140668 Forming Structures on Resistive Substrates  
A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a...
US20140217557 Method and Apparatus for a Seal Ring Structure  
A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to...
US20140131840 WAFER AND METHOD OF MANUFACTURING THE SAME  
A wafer includes a first die, a second die, and a scribe lane located between the first die and the second die. The scribe lane includes a first doped silicon region, and does not directly contact...
Matches 1 - 50 out of 254 1 2 3 4 5 6 >