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US20120196425 |
High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials
When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization...
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US20120223407 |
Superior Integrity of High-K Metal Gate Stacks by Capping STI Regions
When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the...
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US20130087880 |
MEMS DEVICE AND METHOD OF MANUFACTURE
A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels,...
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US20120126359 |
Structure to Reduce Etching Residue
A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal...
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US20120276707 |
METHOD FOR FORMING TRENCH ISOLATION
A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating...
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US20070042560 |
Method for growing thin nitride film onto substrate and thin nitride film device
The present invention provides a method for growing a thin nitride film over a substrate and a thin nitride film device, in which the polarity of the thin nitride film can be controlled by a low...
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US20090243029 |
METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric...
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US20100029057 |
SILICONE RESIN COMPOSITION AND METHOD OF FORMING A TRENCH ISOLATION
A silicone resin which is represented by the following rational formula (1) and solid at 120° C.: (H2SiO)n(HSiO1.5)m(SiO2)k (1) wherein n, m and k are each a number, with the proviso that, when ...
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US20120292664 |
Integrated Circuit (IC) Chip Having Both Metal and Silicon Gate Field Effect Transistors (FETs) and Method of Manufacture
Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a...
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US20090189216 |
SEMICONDUCTOR COMPONENT INCLUDING A DRIFT ZONE AND A DRIFT CONTROL ZONE
Semiconductor component including a drift region and a drift control region. One embodiment provides a drift zone and a drift control zone. A drift control zone dielectric is arranged between the...
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US20120208341 |
Alignment Marks for Polarized Light Lithography and Method for Use Thereof
Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the...
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US20090321870 |
SHUTTLE WAFER AND METHOD OF FABRICATING THE SAME
A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the...
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US20120126336 |
Isolation FET for Integrated Circuit
An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the...
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US20080237573 |
Mechanism for forming a remote delta doping layer of a quantum well structure
A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
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US20090209081 |
Silicon Dioxide Thin Films by ALD
Methods are provided for depositing silicon dioxide containing thin films on a substrate by atomic layer deposition ALD. By using disilane compounds as the silicon source, good deposition rates and...
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US20100025726 |
Lateral Devices Containing Permanent Charge
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges...
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US20120190167 |
MECHANISMS OF DOPING OXIDE FOR FORMING SHALLOW TRENCH ISOLATION
The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such...
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US20090298246 |
TECHNIQUES FOR FABRICATING A NON-PLANAR TRANSISTOR
Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may...
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US20080283925 |
Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement
In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of...
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US20120074496 |
Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same
Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing...
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US20110250731 |
PREFERENTIAL DIELECTRIC GAPFILL
Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric...
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US20080026540 |
Integration for buried epitaxial stressor
Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a...
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US20070107655 |
Sub-resolutional laser annealing mask
A mask with sub-resolution aperture features and a method for smoothing an annealed surface using a sub-resolution mask pattern are provided. The method comprises: supplying a laser beam having a...
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US20110177669 |
METHOD OF CONTROLLING TRENCH MICROLOADING USING PLASMA PULSING
Methods and apparatus for controlling microloading, such as within cell microloading between adjacent cells or isolated/dense microloading between areas of isolated or dense features during shallow...
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US20070243692 |
Methods of filling isolation trenches for semiconductor devices and resulting structures
The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped...
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US20090079005 |
Integrated Circuits and Methods of Design and Manufacture Thereof
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of...
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US20120319230 |
ETCHING NARROW, TALL DIELECTRIC ISOLATION STRUCTURES FROM A DIELECTRIC LAYER
Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor...
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US20070210403 |
Isolation regions and their formation
A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to...
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US20090001503 |
SEMICONDUCTOR DEVICE HAVING FLOATING BODY ELEMENT AND BULK BODY ELEMENT AND METHOD OF MANUFACTURING THE SAME
A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body...
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US20060228864 |
Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using Epi-Si growth process
A semiconductor device having a transistor and a storage capacitor. The transistor includes source and drain regions formed on a substrate. The storage capacitor is coupled to the transistor. The...
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US20090166810 |
Semiconductor Device Crack-Deflecting Structure and Method
The invention relates to microelectronic semiconductor devices, and to mass-production of the same on semiconductor wafers with novel crack-deflecting structures and methods. According to the...
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US20080017949 |
Front-rear contacts of electronics devices with induced defects to increase conductivity thereof
An electronic device is proposed. The device is integrated in a chip including at least one stacked layer having a front surface and a rear surface opposite the front surface, the device including:...
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US20120083093 |
ISOLATION STRUCTURE FOR A MEMORY CELL USING AL2O3 DIELECTRIC
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated...
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US20090072341 |
BURIED LOW-RESISTANCE METAL WORD LINES FOR CROSS-POINT VARIABLE-RESISTANCE MATERIAL MEMORIES
Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode....
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US20090315114 |
STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS
Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier...
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US20100090278 |
High-Voltage Transistor with High Current Load Capacity and Method for its Production
An isolation area (10) is provided over a drift region (12) with a spacing (d) to a contact area (4) provided for a drain connection (D). The isolation area is used as an implantation mask, in...
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US20090315139 |
PATTERNING METHOD AND SEMICONDUCTOR DEVICE
A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate,...
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US20080261374 |
SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE
A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer...
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US20080124888 |
Semiconductor device isolation structures
Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a...
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US20080261375 |
Method of Forming a Semiconductor Device Having a Dummy Feature
A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the...
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US20070155116 |
Method of measuring shifted epitaxy layer by buried layer
A method of measuring a shifted extent of a shifted epitaxy layer by an N+ buried layer using difference between contact resistances is described. An N-type buried layer comprising a stepped...
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US20080254590 |
Fabrication process for silicon-on-insulator field effect transistors using high temperature nitrogen annealing
Disclosed is a method of fabricating a silicon-on-insulator (SOI) device that enables high device densities and mitigates variances in carrier mobility and saturation drain current (Idsat). The...
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US20060270178 |
Method for manufacturing high-frequency signal transmission circuit and high-frequency signal transmission circuit device
A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a...
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US20080149936 |
PROCESS FOR INTEGRATNG A III-N TYPE COMPONENT ON A (001) NOMINAL SILICIUM SUBSTRATE
A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual...
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US20050079682 |
Method of manufacturing void-free shallow trench isolation layer
Provided is a method of manufacturing a shallow trench isolation (STI) film without voids or added processes. In one embodiment, the method of manufacturing an STI film includes forming a pad oxide...
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US20090148990 |
Semiconductor devices and methods of forming the same
A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap...
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US20100009546 |
Aminosilanes for Shallow Trench Isolation Films
The present invention is a process for spin-on deposition of a silicon dioxide-containing film under oxidative conditions for gap-filling in high aspect ratio features for shallow trench isolation...
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US20120295414 |
METHODS FOR PRODUCING STACKED ELECTROSTATIC DISCHARGE CLAMPS
Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second...
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US20050272220 |
Ultraviolet curing process for spin-on dielectric materials used in pre-metal and/or shallow trench isolation applications
A UV curing process for a dielectric material used in pre-metal and shallow trench isolation applications comprises coating a suitable dielectric material onto a substrate; and exposing the...
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US20070054463 |
Method for forming spacers between bitlines in virtual ground memory array and related structure
According to one exemplary embodiment, a method of fabricating a virtual ground memory array, which includes bitlines situated in a substrate, includes forming at least one recess in the substrate...
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