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US20110291235 COPPER INTERCONNECTION STRUCTURE WITH MIM CAPACITOR AND A MANUFACTURING METHOD THEREOF  
The present invention discloses a copper interconnection structure with MIM capacitor and a manufacturing method thereof. The method firstly makes a copper conductive pattern in a copper...
US20130011990 Methods of Making Crystalline Tantalum Pentoxide  
There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with...
US20150158719 MEMS Device with Sealed Cavity and Method for Fabricating Same  
Disclosed is a MEMS device having lower and upper chambers with a similar pressure and/or a similar gaseous chemistry. The MEMS device includes a top MEMS plate and a bottom MEMS plate. The MEMS...
US20120112259 INTEGRATED CIRCUIT WITH PROTECTION FROM COPPER EXTRUSION  
An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The...
US20130130467 RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES  
A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces...
US20130093049 High Productivity Combinatorial Dual Shadow Mask Design  
Dual shadow mask design can overcome the size and resolution limitations of shadow masks to provide capacitor structures with small effective areas. The capacitor structures have bottom and top...
US20130249112 PASSIVE WITHIN VIA  
A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of...
US20130043556 SIZE-FILTERED MULTIMETAL STRUCTURES  
A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A...
US20130102121 Oxygen Diffusion Barrier Comprising Ru  
A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing...
US20100327902 Power saving termination circuits for dram modules  
The present invention provides power saving methods by replacing termination resistors used to support SSTL DRAM interfaces with RC termination circuits; the RC termination circuits consumes...
US20130001746 MULTI-FINGER CAPACITOR WITH REDUCED SERIES RESISTANCE  
An electronic die includes a multi-finger capacitor including a first electrically conductive plate including a plurality of first metal fingers joined together by a first metal base, and a second...
US20150093873 INDUCTOR DEVICE AND FABRICATION METHOD  
Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar...
US20130328164 INDUCTOR DEVICE AND FABRICATION METHOD  
Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar...
US20120104552 Capacitors in Integrated Circuits and Methods of Fabrication Thereof  
In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are...
US20120199947 METHOD FOR MANUFACTURING AND REOXIDIZING A TIN/TA2O5/TIN CAPACITOR  
A method for manufacturing a TiN/Ta2O5/TiN capacitor, including the steps of forming a Ta2O5 layer on a TiN support by a plasma-enhanced atomic layer deposition method, or PEALD; and submitting...
US20120181661 METHOD FOR TUNING THE TRHESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE  
A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches...
US20110304014 PASSIVE INTEGRATED CIRCUIT  
A passive integrated circuit formed on a substrate, including contact areas of a conductive material specifically capable of receiving bonding pads, wherein the conductive material further creates...
US20140070363 ELECTRONIC ANTI-FUSE  
An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above...
US20120012976 FUSE STRUCTURE HAVING CRACK STOP VOID, METHOD FOR FORMING AND PROGRAMMING SAME, AND DESIGN STRUCTURE  
The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a...
US20150179731 EMBEDDED THREE-DIMENSIONAL CAPACITOR  
An embedded capacitor is provided that includes a substrate having a dielectric-filled window. A metal-insulator-metal structure lines a plurality of vias extending through the dielectric-filled...
US20130175664 Power Management Module and Method of Manufacture  
A power management module, provides an inductor including one or more electrical conductors disposed around a ferromagnetic ceramic element including one or more metal oxides having fluctuations...
US20150028449 NANOPARTICLES FOR MAKING SUPERCAPACITOR AND DIODE STRUCTURES  
Structures and methods of making a supercapacitor may include a first electrode comprising a first conductive plate and a 3-dimensional (3D) aggregate of sintered nanoparticles electrically...
US20130009279 INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS  
Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator,...
US20150206837 TOROID INDUCTOR IN REDISTRIBUTION LAYERS (RDL) OF AN INTEGRATED DEVICE  
Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal...
US20120190165 Creating Integrated Circuit Capacitance From Gate Array Structures  
Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets)...
US20140357045 eFUSE AND METHOD OF FABRICATION  
An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a...
US20120187529 eFUSE AND METHOD OF FABRICATION  
An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a...
US20070037358 Apparatus for etching a glass substrate  
An apparatus for etching a glass substrate includes a container for receiving an etching solution and at least two rollers disposed in the container. The at least two rollers may face with each...
US20150263082 INDUCTOR STRUCTURES WITH IMPROVED QUALITY FACTOR  
In one embodiment, an inductor structure is provided. The inductor structure includes a first elongated segment and a second elongated segment. The first elongated segment runs parallel to a...
US20080303117 Integrated circuit with multi-stage matching circuit  
An integrated circuit with a multi-stage matching circuit with an inductive conductive structures with a first end and a second end in the integrated circuit and a capacitor structure in the...
US20120118739 DEVICES AND METHODS FOR SEQUENCING NUCLEIC ACIDS  
Methods and devices for sequencing nucleic acids are disclosed herein. Devices are also provided herein for measuring DNA with nano-pores sized to allow DNA to pass through the nano-pore. The...
US20120329235 WET ETCH AND CLEAN CHEMISTRIES FOR MoOx  
A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting...
US20110168965 Reducing Drift in Chalcogenide Devices  
Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with...
US20130234099 NON-VOLATILE STORAGE WITH METAL OXIDE SWITCHING ELEMENT AND METHODS FOR FABRICATING THE SAME  
Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be...
US20150115405 WIRELESS INTERCONNECTS IN AN INTERPOSER  
Some implementations provide an interposer that includes a substrate, a first passive device in the substrate, and a second passive device. The first passive device includes a first set of through...
US20150187709 METAL FUSE BY TOPOLOGY  
Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a...
US20140191365 DEVICE DESIGN FOR PARTIALLY ORIENTED RUTILE DIELECTRICS  
Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of...
US20110212593 CMP Process Flow for MEMS  
The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line...
US20150130681 3D ANTENNA FOR INTEGRATED CIRCUITS  
An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more...
US20140299964 ON-CHIP INDUCTOR USING REDISTRIBUTION LAYER AND DUAL-LAYER PASSIVIATION  
A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a...
US20120322222 METHOD FOR IMPROVING CAPACITANCE UNIFORMITY IN A MIM DEVICE  
A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step...
US20140117497 Decoupling Capacitors For Integrated Circuits  
On-chip decoupling capacitors and methods for placing the same are disclosed in which designated spaces are created between the active circuits to insert designated capacitor cells. The designated...
US20100041232 Adjustable dummy fill  
A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is...
US20140231957 COMPLEMENTARY BACK END OF LINE (BEOL) CAPACITOR  
A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer...
US20110147891 CAPACITOR AND A METHOD OF MANUFACTURING THE SAME  
A capacitor (110), wherein the capacitor (110) comprises a capacitor dielectric (112) comprising a dielectric matrix (114) of a first value of permittivity, and a plurality of nanoclusters (116)...
US20050071970 Manufacturing method for electrodes that inhibit corona effect on ceramic capacitor  
A manufacturing method for electrodes that inhibit corona effect on ceramic capacitor is disclosed. It is mainly to coat the two electrodes of a ceramic capacitor (including AC ceramic capacitor...
US20130328163 INDUCTOR DEVICE AND FABRICATION METHOD  
Various embodiments provide inductor devices and fabrication methods. In one embodiment, an inductor device can include a first dielectric layer disposed on a semiconductor substrate; a first...
US20150200242 METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR  
A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are...
US20110306174 Patterning Method for High Density Pillar Structures  
A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first...
US20130095632 Enhanced Work Function Layer Supporting Growth of Rutile Phase Titanium Oxide  
This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for...