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US20110272765 MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION  
A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.
US20110156099 ENHANCED CONFINEMENT OF SENSITIVE MATERIALS OF A HIGH-K METAL GATE ELECTRODE STRUCTURE  
When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide...
US20120156837 Sacrificial Spacer Approach for Differential Source/Drain Implantation Spacers in Transistors Comprising a High-K Metal Gate Electrode Structure  
In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any...
US20050054164 Strained silicon MOSFETs having reduced diffusion of n-type dopants  
Processing is performed during fabrication of a strained silicon NMOS device to create point defects in silicon germanium portions of source regions, and optionally of drain regions, prior to...
US20110034000 SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE  
A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and...
US20110101427 TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT  
When forming a sophisticated high-k metal gate stack in an early manufacturing stage, the dielectric cap layer may be efficiently removed without unduly affecting the drain and source extension...
US20140021539 Power Transistor with High Voltage Counter Implant  
Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and...
US20140252429 CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH  
Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is...
US20110129980 CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL  
Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a...
US20130168743 STRAINED TRANSISTOR STRUCTURE  
A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.
US20090294850 METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE  
The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants,...
US20050070082 Semiconductor device having a nickel/cobalt silicide region formed in a silicon region  
By forming a buried nickel silicide layer followed by a cobalt silicide layer in silicon-containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of...
US20070254444 A SEMICONDUCTOR DEVICE HAVING STRESSED ETCH STOP LAYERS OF DIFFERENT INTRINSIC STRESS IN COMBINATION WITH PN JUNCTIONS OF DIFFERENT DESIGN IN DIFFERENT DEVICE REGIONS  
By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may...
US20050208726 Spacer approach for CMOS devices  
A semiconductor device having a graded source/drain region for use in CMOS devices is provided. The semiconductor device is formed by utilizing a spacer and a sacrificial spacer as masks. The...
US20080124880 FET STRUCTURE USING DISPOSABLE SPACER AND STRESS INDUCING LAYER  
Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form...
US20050090067 Silicide formation for a semiconductor device  
A polysilicon line (22), used e.g. as a gate, has a portion (30) amorphized by implanting (19) particles having a relatively large atomic mass. The amorphized portion is used to form a metal...
US20140231907 METHODS OF INDUCING A DESIRED STRESS IN THE CHANNEL REGION OF A TRANSISTOR BY PERFORMING ION IMPLANTATION/ANNEAL PROCESSES ON THE GATE ELECTRODE  
One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that...
US20060017118 Semiconductor device having spacer pattern and method of forming the same  
The present invention provides a semiconductor device having a spacer pattern and methods of forming the same that includes a lower interconnection pattern on a semiconductor substrate. A lower...
US20100317170 METHOD FOR IMPROVING THE THERMAL STABILITY OF SILICIDE  
An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an interface layer 200 over the...
US20080265291 MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS  
Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source...
US20110095368 ELECTROSTATIC DISCHARGE PROTECTION DEVICE  
An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device preferably includes a first transistor, a second transistor, and an electrostatic discharge...
US20070029608 Offset spacers for CMOS transistors  
An offset spacer for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate, and an offset mask layer is formed over the surface of the gate electrode...
US20140015009 TUNNEL TRANSISTOR WITH HIGH CURRENT BY BIPOLAR AMPLIFICATION  
A tunnel-effect transistor the drain region of which includes a first zone doped with a doping of a first type, and a second zone doped with a doping of a second type forming a junction with the...
US20110269286 HEAVILY DOPED REGION IN DOUBLE-DIFFUSED SOURCE MOSFET (LDMOS) TRANSISTOR AND A METHOD OF FABRICATING THE SAME  
A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and...
US20120003806 METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE  
A method for fabricating an integrated device is disclosed. A sacrificial gate stack is provided with a line width narrower than the target width of the final gate structure. After performing a...
US20070032026 Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing  
A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket...
US20140048874 MOS WITH RECESSED LIGHTLY-DOPED DRAIN  
LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate...
US20060240631 Method for manufacturing a solid-state image capturing device and electric information device  
A method for manufacturing a solid-state image capturing device, in which at least one electric charge detection section detects each respective one of a plurality of electric charges...
US20090224739 HEAVILY DOPED REGION IN DOUBLE-DIFFUSED SOURCE MOSFET (LDMOS) TRANSISTOR AND A METHOD OF FABRICATING THE SAME  
A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and...
US20090179280 HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDUCE DAMAGE  
Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due...
US20080023752 BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT  
An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate;...
US20130230960 STRUCTURE FABRICATION METHOD  
A structure fabrication method. A provided structure includes a gate dielectric region on the substrate and a gate electrode region on the gate dielectric region. Atoms are implanted in a top...
US20100045365 TWO TERMINAL QUANTUM DEVICE USING MOS CAPACITOR STRUCTURE  
A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either...
US20100065925 LOCAL CHARGE AND WORK FUNCTION ENGINEERING ON MOSFET  
The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the...
US20060040450 Source/drain structure for high performance sub 0.1 micron transistors  
An asymmetric transistor structure comprising a gate structure with a drain halo ion implantation region, without any halo ion implantation region source region is provided. Methods of forming a...
US20090246927 INCREASING STRESS TRANSFER EFFICIENCY IN A TRANSISTOR BY REDUCING SPACER WIDTH DURING THE DRAIN/SOURCE IMPLANTATION SEQUENCE  
By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to...
US20080166849 LDMOS device and method  
An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the...
US20080242039 METHOD OF ENHANCING DOPANT ACTIVATION WITHOUT SUFFERING ADDITIONAL DOPANT DIFFUSION  
A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate,...
US20050048731 Siliciding spacer in integrated circuit technology  
A method of forming an integrated circuit and a structure therefore is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. Shallow...
US20110207282 Methods for Producing a Tunnel Field-Effect Transistor  
A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.
US20140070333 SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS  
A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional...
US20140084367 Extended Source-Drain MOS Transistors And Method Of Formation  
A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating...
US20100025742 TRANSISTOR HAVING A STRAINED CHANNEL REGION CAUSED BY HYDROGEN-INDUCED LATTICE DEFORMATION  
A lattice distortion may be achieved by incorporating a hydrogen species into a semiconductor material, such as silicon, without destroying the lattice structure. For example, by incorporating the...
US20090059111 LCD DRIVER IC AND METHOD FOR MANUFACTURING THE SAME  
Disclosed is an LCD driver IC. The LCD driver IC can include a first conductive type well formed in a substrate, a second conductive type drift region formed in the first conductive type well, a...
US20070161198 Transistors With Gate Stacks Having Metal Electrodes  
A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially...
US20060099762 Method for manufacturing mosfet device in peripheral region  
Disclosed is a method for manufacturing a MOSFET device in a peripheral region capable of avoiding degradation of electrical characteristics of the MOSFET device in the peripheral region. The...
US20060024938 Method for reducing metal silicide excessive encroachment defects in the manufacture of a semiconductor device having silicided source/drain regions  
The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor device, and a semiconductor...
US20090203182 Method of manufacturing transistor having metal silicide and method of manufacturing a semiconductor device using the same  
In a method of manufacturing a transistor and a method of manufacturing a semiconductor device using the same, the method may include forming a preliminary metal silicide pattern on a...
US20120196422 Stress Memorization Technique Using Gate Encapsulation  
Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein a stress memorization technique is used to enhance the...
US20100144110 Method of forming a MOS transistor  
A method of forming a MOS transistor, in which, a co-implantation is performed to implant a carbon co-implant into a source region and a drain region or a halo implanted region to effectively...

Matches 1 - 50 out of 212 1 2 3 4 5 >