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US20150014786 HIGH PERFORMANCE POWER CELL FOR RF POWER AMPLIFIER  
A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate...
US20120319188 ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE AND A GATE TAP AND A PROCESS OF FORMING THE SAME  
An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region...
US20130032876 Replacement Gate ETSOI with Sharp Junction  
A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer...
US20110104861 INTEGRATED COMPLEMENTARY LOW VOLTAGE RF-LDMOS  
Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to...
US20150162338 Methods of Forming Sidewall Gates  
A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate...
US20130277735 WAFER LEVEL MOSFET METALLIZATION  
Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having...
US20140042524 Device with a Vertical Gate Structure  
A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum...
US20150137067 NANOWIRE MOSFET WITH DIFFERENT SILICIDES ON SOURCE AND DRAIN  
A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET...
US20100320461 INTEGRATION OF SENSE FET INTO DISCRETE POWER MOSFET  
A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical...
US20120068231 VERTICAL DISCRETE DEVICES WITH TRENCH CONTACTS AND ASSOCIATED METHODS OF MANUFACTURING  
The present technology is related generally to vertical discrete devices with a trench at the topside of the vertical discrete devices. The trench is filled with a conducting material. In this...
US20060063334 Fin FET diode structures and methods for building  
FinFET diode structures and methods are provided for building the FinFET diode structures. A FinFET diode structure is created by implanting a diffusion Fin on a first side with a P+ dopant and on...
US20130234113 QUANTUM WELL MOSFET CHANNELS HAVING LATTICE MISMATCH WITH METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS  
Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel...
US20150031180 VERTICAL CHANNEL TRANSISTOR WITH SELF-ALIGNED GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME  
A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on...
US20150014706 Vertical Hetero Wide Bandgap Transistor  
A vertical hetero transistor provides a wide bandgap, increases the breakdown voltage or reduces the on resistance of the switching transistor or both.
US20090302374 Differential Nitride Pullback to Create Differential NFET to PFET Divots for Improved Performance Versus Leakage  
Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide...
US20050077553 Methods of forming multi fin FETs using sacrificial fins and devices so formed  
Methods of forming multi fin Field Effect Transistors (FET) can include forming a first fin having opposing sidewalls protruding from a substrate and epitaxially growing second fins on the...
US20150118809 METHOD OF MAKING STRUCTURE HAVING A GATE STACK  
A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and...
US20130062675 PILLARS FOR VERTICAL TRANSISTORS  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
US20140045310 METHOD OF MAKING STRUCTURE HAVING A GATE STACK  
A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric...
US20090256187 SEMICONDUCTOR DEVICE HAVING VERTICAL PILLAR TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a...
US20120235240 HIGH DENSITY SIX TRANSISTOR FINFET SRAM CELL LAYOUT  
Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking...
US20150017770 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer...
US20110227147 SUPER JUNCTION DEVICE WITH DEEP TRENCH AND IMPLANT  
RESURF effect devices with both relatively deep trenches and relatively deep implants are described herein. Also, methods of fabricating such devices are described herein. A RESURF effect device...
US20130193502 MEDIUM VOLTAGE MOSFET DEVICE  
A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of...
US20070052012 Vertical tunneling nano-wire transistor  
A vertical nano-wire transistor is formed on a substrate out of a vertical pillar having active regions of opposing conductivity in opposite ends of the pillar. In one embodiment, the source...
US20130175606 INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME  
A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain...
US20120261753 DMOS Transistor with a Slanted Super Junction Drift Structure  
A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with...
US20140193958 TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE  
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an...
US20150137079 VERTICAL TUNNEL FIELD EFFECT TRANSISTOR (FET)  
Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical...
US20140021532 VERTICAL TUNNEL FIELD EFFECT TRANSISTOR (FET)  
Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical...
US20090001337 Phase Change Memory Cell with Vertical Transistor  
A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is...
US20150162430 PLANAR VERTICAL DMOS TRANSISTOR WITH A CONDUCTIVE SPACER STRUCTURE AS GATE  
A planar vertical DMOS transistor uses a conductive spacer structure formed on the sides of a dielectric structure as the gate of the transistor. The planar vertical DMOS transistor with a...
US20140110788 Power Converter Package Including Top-Drain Configured Power FET  
In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and...
US20150097225 TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET  
A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the...
US20090298246 TECHNIQUES FOR FABRICATING A NON-PLANAR TRANSISTOR  
Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may...
US20060258087 Methods of forming vertical transistor structures  
The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention...
US20100044792 Charged balanced devices with shielded gate trench  
This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a...
US20080142811 MOSFET devices and methods of fabrication  
A vertical MOSFET is disclosed. The MOSFET includes a gate dielectric region, a drift region having a drift region dopant concentration profile of a first conductivity type, and a JFET region...
US20090057755 SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME  
Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate...
US20140239385 FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME  
A Field Effect Transistor (FET) and a method of manufacturing the same are provided. The FET may include a substrate; a source and a drain, one of which is formed on a bulge formed on a top...
US20100295023 FIELD EFFECT TRANSISTOR FABRICATION FROM CARBON NANOTUBES  
Methods and apparatus for an electronic device such as a field effect transistor. One embodiment includes fabrication of an FET utilizing single walled carbon nanotubes as the semiconducting...
US20130001694 LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE  
A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first...
US20110180867 METAL TRANSISTOR DEVICE  
The present invention is related to a depletion or enhancement mode metal transistor in which the channel regions of a transistor device comprises a thin film metal or metal composite layer formed...
US20080203470 Lateral compensation component  
A transistor is provided which includes a lateral compensation component. The lateral compensation component includes a plurality of n (or n−) layer/p (or p−) layer pairs, wherein adjacent ones of...
US20080124869 METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES  
Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate...
US20140284703 VERTICAL DOUBLE-DIFFUSION MOS AND MANUFACTURING TECHNIQUE FOR THE SAME  
In one embodiment, a method of making a VDMOS transistor can include: (i) etching an oxide layer formed on a surface of an epitaxial structure to define an active region of the VDMOS; (ii)...
US20130140629 INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL  
A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate...
US20110101449 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD  
Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain...
US20140001520 CONTACT RESISTANCE REDUCED P-MOS TRANSISTORS EMPLOYING GE-RICH CONTACT LAYER  
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a...
US20140264557 SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS  
A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including...