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US20160322508 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A method for producing a semiconductor device includes forming a first fin-shaped silicon layer and a second fin-shaped silicon layer on a substrate using a sidewall formed around a dummy pattern...
US20160322459 NANO-TUBE MOSFET TECHNOLOGY AND DEVICES  
This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a...
US20160308029 PREPARATION METHOD FOR POWER DIODE  
A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20)...
US20160307916 Three-Dimensional Charge Trapping NAND Cell with Discrete Charge Trapping Film  
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed...
US20160300847 INTEGRATED CIRCUIT DEVICE INCLUDING POLYCRYSTALLINE SEMICONDUCTOR FILM AND METHOD OF MANUFACTURING THE SAME  
An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which are formed on a substrate and...
US20160293423 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE  
A method for manufacturing a silicon carbide semiconductor device includes steps below. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main...
US20160276160 Silicide Region of Gate-All-Around Transistor  
The disclosure relates to a semiconductor device and methods of forming same. A representative structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the...
US20160268427 Method for Inducing Strain in Vertical Semiconductor Columns  
A vertical Metal-Oxide-Semiconductor (MOS) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material. An oxide ring extends from an outer...
US20160247899 POWER MOSFET DEVICE STRUCTURE FOR HIGH FREQUENCY APPLICATIONS  
This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said...
US20160247720 Top Metal Pads as Local Interconnectors of Vertical Transistors  
An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top...
US20160247679 MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE, PATTERN GENERATING METHOD AND NONTRANSITORY COMPUTER READABLE MEDIUM STORING A PATTERN GENERATING PROGRAM  
According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in...
US20160240653 Medium High Voltage MOSFET Device  
A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of...
US20160240555 THREE-DIMENSIONAL (3D) SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING 3D SEMICONDUCTOR DEVICES  
A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection...
US20160240549 Method For Manufacturing Semiconductor Device  
According to one embodiment, a method for manufacturing a semiconductor device includes forming a first film on a multilayer body including two or more stacked films. One stacked film includes a...
US20160233316 Method of Manufacturing a Spacer Supported Lateral Channel FET  
A semiconductor device is manufactured by forming a plurality of trenches extending into a semiconductor material from a first main surface of the semiconductor material to form mesas of...
US20160225892 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET...
US20160225784 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
According to one embodiment, a method for manufacturing a semiconductor device includes modifying surfaces of the first mask films and surfaces of the second mask films. The method includes...
US20160218191 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
A method of fabricating a semiconductor device includes forming fin-shaped semiconductor layers on a semiconductor substrate. First and second pillar-shaped semiconductor layers are formed, and...
US20160204251 PILLAR-SHAPED SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR  
A SiO2 layer is formed at a middle of a Si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the SiO2...
US20160204205 SOURCE MATERIAL FOR ELECTRONIC DEVICE APPLICATIONS  
Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical...
US20160204192 Semiconductor Device and Manufacturing Method for the Semiconductor Device  
In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a...
US20160204123 Method of fabricating three-dimensional semiconductor devices, and three-dimensional semiconductor devices thereof  
Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising providing a substrate and forming a plurality of layers over the...
US20160204122 THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PLURAL SELECT GATE TRANSISTORS HAVING DIFFERENT CHARACTERISTICS AND METHOD OF MAKING THEREOF  
A stack of material layers includes first material layers, second material layers located between a respective pair of an overlying first material layer and an underlying first material layer, and...
US20160204117 VERTICAL NAND AND METHOD OF MAKING THEREOF USING SEQUENTIAL STACK ETCHING AND SELF-ALIGNED LANDING PAD  
Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal...
US20160197181 SEMICONDUCTOR DEVICE WITH AN SGT AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device includes a P+ region and an N+ region functioning as sources of SGTs and disposed in top portions of Si pillars formed on an i-layer substrate. Connections between a power...
US20160197164 Method of Producing a Semiconductor Arrangement  
A semiconductor arrangement is produced by providing a semiconductor carrier of a second conduction type and epitaxially growing a first semiconductor zone of a first conduction type on the...
US20160197163 MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS  
A screen oxide film is formed on an n− drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The...
US20160197140 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
A MOS semiconductor device has a MOS structure, including a p− region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in...
US20160197092 VERTICAL MEMORY DEVICES AND RELATED METHODS OF MANUFACTURE  
A vertical semiconductor memory device having conducting and charge-trapping columns separated by columns of holes is disclosed. The columns are formed in layers of alternating conducting and...
US20160197090 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked mask on a layer to be processed. The stacked mask has a plurality of intermediate films...
US20160197041 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
A memory device comprises a first conductive stripe, a first memory layer, a first conductive pillar, a first dielectric layer and a first conductive plug. The first conductive strip extends along...
US20160190313 LOCAL BURIED CHANNEL DIELECTRIC FOR VERTICAL NAND PERFORMANCE ENHANCEMENT AND VERTICAL SCALING  
A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk...
US20160190312 VERTICAL GATE ALL-AROUND TRANSISTOR  
Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to...
US20160190282 VERTICAL TRANSISTOR DEVICES FOR EMBEDDED MEMORY AND LOGIC TECHNOLOGIES  
Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial...
US20160190155 ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first...
US20160190154 METHODS FOR MAKING A TRIM-RATE TOLERANT SELF-ALIGNED CONTACT VIA STRUCTURE ARRAY  
A stack is formed over a substrate, which comprises an alternating plurality of first material layers including a first material and second material layers including a second material. A patterned...
US20160190153 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of fin structures, a plurality of conductor liner layers, a...
US20160190150 NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF  
A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory...
US20160190127 HIGH PERFORMANCE POWER CELL FOR RF POWER AMPLIFIER  
A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a Schottky MOSFET formed in an N-Well in the same P-Substrate with a...
US20160181374 Silicon Carbide Semiconductor Device and Method for Manufacturing the Same  
A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first...
US20160181373 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in...
US20160181365 SEMICONDUCTOR DEVICES HAVING CHANNEL REGIONS WITH NON-UNIFORM EDGE  
A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed...
US20160181362 Silicide Regions in Vertical Gate All Around (VGAA) Devices and Methods of Forming Same  
An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the...
US20160181323 CELL PILLAR STRUCTURES AND INTEGRATED FLOWS  
Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a...
US20160181272 Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel  
Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are formed in horizontal layers of...
US20160181271 METHODS OF FABRICATING MEMORY DEVICE WITH SPACED-APART SEMICONDUCTOR CHARGE STORAGE REGIONS  
Methods of fabricating semiconductor devices, such as monolithic three-dimensional NAND memory string devices, include selectively forming semiconductor material charge storage regions over first...
US20160181269 THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME  
A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a...
US20160181264 THREE DIMENSIONAL NAND MEMORY HAVING IMPROVED CONNECTION BETWEEN SOURCE LINE AND IN-HOLE CHANNEL MATERIAL AS WELL AS REDUCED DAMAGE TO IN-HOLE LAYERS  
A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material...
US20160172494 MEMORY CELL ARRAY AND CELL STRUCTURE THEREOF  
A memory device includes a substrate and a memory array. The substrate has a continuous active region. The memory array is disposed in the continuous active region of the substrate and includes a...
US20160172373 Memory Arrays and Methods of Fabricating Integrated Structures  
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are...