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US20140346588 SUPERJUNCTION POWER DEVICE AND MANUFACTURING METHOD  
A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with...
US20140264579 Field Effect Transistor Devices with Buried Well Regions and Epitaxial Layers  
A method of forming a transistor device includes providing a drift layer having a first conductivity type and an upper surface, forming first regions in the drift layer and adjacent the upper...
US20140219017 CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME  
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially...
US20140141584 POWER SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING THE SAME  
A power semiconductor device includes: a drain region of a first conductive type; a drift region of a first conductive type formed on the drain region; a first body region of a second conductive...
US20140073099 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device has a vertical channel and includes a first tunnel insulating layer adjacent to a blocking insulating layer, a third tunnel insulating layer adjacent to a channel pillar,...
US20140035025 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
A nonvolatile memory device includes a plurality of channel connection layers formed over a substrate; a first gate electrode layer filling a space between the plurality channel connection layers;...
US20140035024 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
A method for fabricating a nonvolatile memory device includes forming a stacked structure over a substrate defining a cell area and a peripheral area and having a source region, the stacked...
US20130270628 Replacement Channels  
The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current...
US20130240983 PROCESS FOR FABRICATING A FIELD-EFFECT TRANSISTOR DEVICE IMPLEMENTED ON A NETWORK OF VERTICAL NANOWIRES, THE RESULTING TRANSISTOR DEVICE, AN ELECTRONIC DEVICE COMPRISING SUCH TRANSISTOR DEVICES AND A PROCESSOR COMPRISING AT LEAST ONE SUCH DEVICE  
A process for fabricating a field-effect transistor device (20) implemented on a network of vertical nanowires (24), includes: producing a source electrode (26) and a drain electrode (30) at each...
US20130240981 TRANSISTOR ARRAY WITH A MOSFET AND MANUFACTURING METHOD  
Disclosed are a semiconductor device and a method for producing a semiconductor device. A MOSFET may have a source region, a drift region and a drain region of a first conductivity type, a body...
US20130228849 NONVOLATILE MEMORY DEVICE AND FABRICATING METHOD THEREOF  
A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate...
US20130221426 ELECTRIC POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME  
A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of...
US20130203229 METHOD OF REDUCING SURFACE DOPING CONCENTRATION OF DOPED DIFFUSION REGION, METHOD OF MANUFACTURING SUPER JUNCTION USING THE SAME AND METHOD OF MANUFACTURING POWER TRANSISTOR DEVICE  
The present invention provides a method of reducing a surface doping concentration of a doped diffusion region. First, a semiconductor substrate is provided. The semiconductor substrate has the...
US20130171787 METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE  
A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at...
US20130153987 ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME  
An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the...
US20120169262 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND POWER MODULE  
A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer...
US20120168819 Semiconductor pillar power MOS  
A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a multi-gate vertical MOS configuration with multi semiconductor pillars, so that the...
US20120146711 Power Domain Controller With Gated Through Silicon Via Having FET With Horizontal Channel  
A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower...
US20120049267 SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a...
US20120049264 NAND Memory Constructions and Methods of Forming NAND Memory Constructions  
Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a...
US20110220980 MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME  
A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second...
US20110171798 LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN  
A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and...
US20110140107 Flat panel display device and method of manufacturing the same  
A flat panel display device including a substrate including first and second regions; an active layer on the first region of the substrate including a semiconductor material; a lower electrode on...
US20110122682 High Density Low Power Nanowire Phase Change Material Memory Device  
A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET)...
US20110012085 METHODS OF MANUFACTURE OF VERTICAL NANOWIRE FET DEVICES  
A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom...
US20100291743 Semiconductor device and method of forming the same  
A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which...
US20100270611 SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR AND PRODUCTION METHOD THEREFOR  
It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor...
US20100264485 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a...
US20100252879 Semiconductor device and method of forming the same  
A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element...
US20100248439 Method of fabricating non-volatile memory device having vertical structure  
A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first...
US20100244123 FIELD-EFFECT TRANSISTOR WITH SELF-LIMITED CURRENT  
A field-effect transistor is integrated in a chip of semiconductor material of a first type of conductivity, which has a first main surface and a second main surface, opposite to each other. The...
US20100224909 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A first well region of a second conductivity type is formed in the portion of the semiconductor layer of the first conductivity type located in an element portion in which a vertical element is...
US20100221882 Nanoelectronic structure and method of producing such  
The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than...
US20100216289 Method of fabricating semiconductor device having metal-semiconductor compound regions  
Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming...
US20100213539 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR  
It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; one of a drain region and a source region formed in contact with a lower part of...
US20100210096 PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE  
It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a...
US20100207202 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device includes a semiconductor substrate, a first insulating film, a second insulating film, and a conductive layer. The semiconductor substrate includes a pillar portion...
US20100207201 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR  
It is intended to provide a semiconductor device comprising a circuit which has a connection between one of a drain region and a source region of a first MOS transistor and one of a drain region...
US20100207198 METHOD FOR FABRICATING A POWER SEMICONDUCTOR DEVICE HAVING A VOLTAGE SUSTAINING LAYER WITH A TERRACED TRENCH FACILITATING FORMATION OF FLOATING ISLANDS  
A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the...
US20100187600 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME  
It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a...
US20100187599 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME  
Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element...
US20100173460 VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME  
A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are...
US20100167481 MANUFACTURING PROCESS OF A VERTICAL-CONDUCTION MISFET DEVICE WITH GATE DIELECTRIC STRUCTURE HAVING DIFFERENTIATED THICKNESS AND VERTICAL-CONDUCTION MISFET DEVICE THUS MANUFACTURE  
According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of...
US20100163949 VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA  
A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor,...
US20100163888 MANUFACTURING PROCESS OF A POWER ELECTRONIC DEVICE INTEGRATED IN A SEMICONDUCTOR SUBSTRATE WITH WIDE BAND GAP AND ELECTRONIC DEVICE THUS OBTAINED  
An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the...
US20100159657 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in...
US20100159656 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE  
A method for fabricating a semiconductor device includes: forming a GaN-based semiconductor layer on a substrate; forming a gate insulating film of aluminum oxide on the GaN-based semiconductor...
US20100155828 FIELD-EFFECT SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME  
A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer,...
US20100148246 Power mosfet device structure for high frequency applications  
This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said...
US20100142294 Vertical Transistor Memory Cell and Array  
A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a...