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US20120196413 METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE  
A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface...
US20150243748 VERTICAL ACCESS DEVICES, SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED METHODS  
A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode...
US20150200308 Field Effect Transistor Constructions And Memory Arrays  
In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region....
US20140231910 Manufacturing a Super Junction Semiconductor Device and Semiconductor Device  
A super junction semiconductor device includes a semiconductor portion with a first surface and a parallel second surface. A doped layer of a first conductivity type is formed at least in a cell...
US20140008714 Three Dimensional NAND Device and Method of Charge Trap Layer Separation and Floating Gate Formation in the NAND Device  
A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking...
US20130313525 Nanowire-based Transistor, Method for Fabricating the Transistor, Semiconductor Component Incorporating the Transistor, Computer Program and Storage Medium Associated with the Fabrication Method  
The transistor (100) comprises a nanowire (101) at least partially forming a channel of the transistor (100), a source contact (102) arranged at a first longitudinal end (103) of the nanowire...
US20130161715 VERTICAL TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING SAME  
A vertical transistor structure includes a substrate, a plurality of pillars located on the substrate and spaced from each other at a selected distance, a gate line and a plurality of conductors....
US20130137229 MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF  
Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells...
US20120211827 METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE  
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped...
US20120091521 MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF  
Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells...
US20100285645 METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES  
Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate...
US20100230733 VERTICAL GATED ACCESS TRANSISTOR  
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a...
US20100144109 TRANSISTOR IN A SEMICONDUCTOR SUBSTRATE HAVING HIGH-CONCENTRATION SOURCE AND DRAIN REGION FORMED AT THE BOTTOM OF A TRENCH ADJACENT TO THE GATE ELECTRODE  
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Trenches are formed in a semiconductor substrate at gate edges. Low-concentration...
US20100015768 Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer  
In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding...
US20090166722 High voltage structures and methods for vertical power devices with improved manufacturability  
This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power...
US20150263037 INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME  
An integrated circuit device according to one embodiment includes a body film, a stopper film, a stacked structure body, a first vertical member and a second vertical member. The stopper film is...
US20150249095 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME  
This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or...
US20150206897 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device according to the embodiment includes a first stack structure. The first stack structure includes at least one first insulating film and a plurality of first conducting films...
US20150179662 COBALT-CONTAINING CONDUCTIVE LAYERS FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE  
A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material...
US20150115348 VERTICAL-TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a...
US20140367770 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device including an active cell region formed over the surface of a silicon substrate and including a vertical MOSFET, a drain electrode formed over the surface of the silicon...
US20140308788 METHOD FOR FABRICATING POWER SEMICONDUCTOR DEVICE  
A substrate having thereon an epitaxial layer is provided. A hard mask having a first opening is formed on the epitaxial layer. A first trench is etched into the epitaxial layer through the first...
US20130341702 Vertical Memory Device and Method for Making Thereof  
Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge...
US20130181185 TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME  
A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate and a drain layer formed in the...
US20130137228 METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE  
A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers...
US20130130454 METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE  
A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers...
US20120267706 Semiconductor device and manufacturing method thereof  
The invention discloses a novel MOSFET device and its implementation method, the device comprising: a substrate; a gate stack structure, on either side of which is eliminated a conventional...
US20120021574 METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE  
A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers...
US20110180843 CHARGE-BALANCE POWER DEVICE COMPRISING COLUMNAR STRUCTURES AND HAVING REDUCED RESISTANCE, AND METHOD AND SYSTEM OF SAME  
An embodiment of a charge-balance power device formed in an epitaxial layer having a first conductivity type and housing at least two columns of a second conductivity type, which extend through...
US20110018056 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is...
US20100317166 METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE  
A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers...
US20100248436 Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns  
In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A...
US20100041195 METHOD OF MANUFACTURING SILICON CARBIDE SELF-ALIGNED EPITAXIAL MOSFET FOR HIGH POWERED DEVICE APPLICATIONS  
A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown...
US20090224310 POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A power semiconductor device capable of transmitting gate signals in all directions (e.g., up-/down-ward/right-/left-ward) on a plane and a method of manufacturing the same. The power...
US20150263115 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME  
A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the...
US20150263074 TRANSISTOR DEVICE AND METHOD OF MAKING THEREOF  
A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material...
US20150243766 METHOD AND APPARATUS FOR POWER DEVICE WITH MULTIPLE DOPED REGIONS  
A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the...
US20150236094 DUAL VERTICAL CHANNEL  
Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a first channel...
US20150228663 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING NICKEL-CONTAINING FILM  
A method of manufacturing a semiconductor device is provided. A substrate including a structure in which a hole is formed is prepared. Precursors including a nickel alkoxide compound are...
US20150214241 THREE-DIMENSIONAL MEMORY AND METHOD OF FORMING THE SAME  
A method of forming a three-dimensional memory is provided. A stacked structure including semiconductor layers and insulating layers arranged alternately is formed on a substrate. The stacked...
US20150155297 METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING DOUBLE-LAYERED BLOCKING INSULATING LAYERS  
Provided is a method of fabricating a semiconductor memory device. The method includes alternately stacking interlayer insulating layers and sacrificial layers on a substrate, forming a channel...
US20150140754 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND POWER MODULE  
A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer...
US20150108562 Three-Dimensional Charge Trapping NAND Cell with Discrete Charge Trapping Film  
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed...
US20150091081 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A semiconductor device includes a semiconductor substrate including a plurality of pillars, a gate electrode formed to surround a lower portion of the pillar and having a top surface lower than a...
US20150079745 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE  
The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first...
US20150079743 METHODS OF FABRICATING A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE  
A method of fabricating a memory device, such as a three-dimensional NAND string, includes forming a trench through a stack of alternating first and second material layers to expose a source...
US20150076588 VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF  
A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal...
US20150048294 VARIABLE RESISTIVE MEMORY DEVICE INCLUDING VERTICAL CHANNEL PMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a...
US20150014764 SUPER JUNCTION MOSFET, METHOD OF MANUFACTURING THE SAME, AND COMPLEX SEMICONDUCTOR DEVICE  
A super junction MOSFET is disclosed. The super junction MOSFET includes a plurality of mutually parallel pn junctions extending in a vertical direction on a first principal surface of an n-type...
US20150008503 Method Of Making A Three-Dimensional Memory Array With Etch Stop  
A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop...