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US20090108339 |
HIGH VOLTAGE TMOS SEMICONDUCTOR DEVICE WITH LOW GATE CHARGE STRUCTURE AND METHOD OF MAKING
A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A...
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US20120119266 |
Stressor in Planar Field Effect Transistor Device
A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a...
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US20110300679 |
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN
A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor portion overlying the underlying doped...
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US20090085111 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor device and a method of manufacturing a semiconductor device. In the semiconductor device, high-concentration n type impurity regions are formed respectively below gate...
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US20090085064 |
HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD
A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a...
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US20090065856 |
Semiconductor device having vertical MOS transistor and method for manufacturing the semiconductor device
In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a...
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US20110281411 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
An amorphous silicon layer and a single crystal silicon layer are formed in an upper portion of a silicon pillar. Then, by performing the selective epitaxial growth method twice, an amorphous...
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US20100102361 |
VERTICAL TRANSISTOR AND FABRICATING METHOD THEREOF AND VERTICAL TRANSISTOR ARRAY
A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar...
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US20090179258 |
NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR DEVICE
A nitride semiconductor device includes: a nitride semiconductor structure portion including a first layer made of an n-type group III nitride semiconductor, a second layer made of a group III...
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US20130020635 |
Semiconductor device with field threshold MOSFET for high voltage termination
This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an...
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US20130009241 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor device includes a drain layer, a drift, a base, a source region, a plurality of gates provided on the drift region, the base, and the source region, and...
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US20120196413 |
METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE
A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface...
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US20130137229 |
MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF
Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at...
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US20120211827 |
METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped...
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US20120091521 |
MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF
Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at...
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US20100285645 |
METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES
Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate...
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US20100230733 |
VERTICAL GATED ACCESS TRANSISTOR
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a...
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US20100144109 |
TRANSISTOR IN A SEMICONDUCTOR SUBSTRATE HAVING HIGH-CONCENTRATION SOURCE AND DRAIN REGION FORMED AT THE BOTTOM OF A TRENCH ADJACENT TO THE GATE ELECTRODE
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Trenches are formed in a semiconductor substrate at gate edges. Low-concentration...
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US20100015768 |
Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer
In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding...
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US20090166722 |
High voltage structures and methods for vertical power devices with improved manufacturability
This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power...
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US20130137228 |
METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE
A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers...
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US20130130454 |
METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE
A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers...
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US20120267706 |
Semiconductor device and manufacturing method thereof
The invention discloses a novel MOSFET device and its implementation method, the device comprising: a substrate; a gate stack structure, on either side of which is eliminated a conventional...
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US20120021574 |
METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE
A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers...
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US20110180843 |
CHARGE-BALANCE POWER DEVICE COMPRISING COLUMNAR STRUCTURES AND HAVING REDUCED RESISTANCE, AND METHOD AND SYSTEM OF SAME
An embodiment of a charge-balance power device formed in an epitaxial layer having a first conductivity type and housing at least two columns of a second conductivity type, which extend through the...
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US20110018056 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is...
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US20100317166 |
METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE
A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers...
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US20100248436 |
Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns
In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A...
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US20100041195 |
METHOD OF MANUFACTURING SILICON CARBIDE SELF-ALIGNED EPITAXIAL MOSFET FOR HIGH POWERED DEVICE APPLICATIONS
A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown...
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US20090224310 |
POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A power semiconductor device capable of transmitting gate signals in all directions (e.g., up-/down-ward/right-/left-ward) on a plane and a method of manufacturing the same. The power semiconductor...
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US20120169262 |
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND POWER MODULE
A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer...
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US20120168819 |
Semiconductor pillar power MOS
A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a multi-gate vertical MOS configuration with multi semiconductor pillars, so that the...
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US20120146711 |
Power Domain Controller With Gated Through Silicon Via Having FET With Horizontal Channel
A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower...
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US20120049267 |
SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a...
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US20120049264 |
NAND Memory Constructions and Methods of Forming NAND Memory Constructions
Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair...
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US20110220980 |
MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME
A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second...
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US20110171798 |
LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN
A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and...
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US20110140107 |
Flat panel display device and method of manufacturing the same
A flat panel display device including a substrate including first and second regions; an active layer on the first region of the substrate including a semiconductor material; a lower electrode on...
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US20110122682 |
High Density Low Power Nanowire Phase Change Material Memory Device
A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET)...
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US20110012085 |
METHODS OF MANUFACTURE OF VERTICAL NANOWIRE FET DEVICES
A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom...
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US20100291743 |
Semiconductor device and method of forming the same
A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which...
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US20100270611 |
SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR AND PRODUCTION METHOD THEREFOR
It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor...
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US20100264485 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a...
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US20100252879 |
Semiconductor device and method of forming the same
A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element...
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US20100248439 |
Method of fabricating non-volatile memory device having vertical structure
A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first...
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US20100244123 |
FIELD-EFFECT TRANSISTOR WITH SELF-LIMITED CURRENT
A field-effect transistor is integrated in a chip of semiconductor material of a first type of conductivity, which has a first main surface and a second main surface, opposite to each other. The...
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US20100224909 |
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A first well region of a second conductivity type is formed in the portion of the semiconductor layer of the first conductivity type located in an element portion in which a vertical element is...
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US20100221882 |
Nanoelectronic structure and method of producing such
The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than...
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US20100216289 |
Method of fabricating semiconductor device having metal-semiconductor compound regions
Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor...
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US20100213539 |
SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; one of a drain region and a source region formed in contact with a lower part of the...
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