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US20110215377 Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region  
A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode...
US20110073943 TRUE CSP POWER MOSFET BASED ON BOTTOM-SOURCE LDMOS  
A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the...
US20120126312 VERTICAL DMOS-FIELD EFFECT TRANSISTOR  
A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET), has a cell structure with a substrate; an epitaxial layer or well of the first conductivity type on the...
US20070048942 Methods of forming field effect transistors on substrates  
The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field...
US20130049100 METHOD OF MAKING A LOW-RDSON VERTICAL POWER MOSFET DEVICE  
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson...
US20120126314 VERTICAL DMOS-FIELD EFFECT TRANSISTOR  
A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first...
US20090148991 Method of fabricating semiconductor device having vertical channel transistor  
A method of fabricating a semiconductor device having a vertical channel transistor, the method including forming a hard mask pattern on a substrate, forming a preliminary active pillar by etching...
US20080173936 ACCESS DEVICE HAVING VERTICAL CHANNEL AND RELATED SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE ACCESS DEVICE  
An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate...
US20080048245 Semiconductor device and manufacturing methods thereof  
A semiconductor device includes: a substrate having a main surface, a first main electrode formed on the main surface of the substrate, a pillar shaped semiconductor layer formed on the first main...
US20140021485 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area...
US20120184077 Configuration and Fabrication of Semiconductor Structure in Which Source and Drain Extensions of Field-effect Transistor Are Defined with Different Dopants  
An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone...
US20080283912 Semiconductor device having super junction structure and method of manufacturing the same  
A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column...
US20130193412 TRANSISTORS AND METHODS OF MANUFACTURING THE SAME  
Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source...
US20090317954 Method for forming vertical channel transistor of semiconductor device  
A method for forming a vertical channel transistor of a semiconductor device includes forming a plurality of pillar patterns over a substrate, forming a gate insulation layer encapsulating the...
US20080179664 SEMICONDUCTOR DEVICE WITH A VERTICAL MOSFET INCLUDING A SUPERLATTICE AND RELATED METHODS  
A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice...
US20100001414 MANUFACTURING A SEMICONDUCTOR DEVICE VIA ETCHING A SEMICONDUCTOR CHIP TO A FIRST LAYER  
A method of manufacturing a semiconductor device. The method includes providing a semiconductor chip including contact elements on a first face and a first layer between the first face and a second...
US20070072416 Method of forming a low resistance semiconductor contact and structure therefor  
In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.
US20110312137 Vertical Power MOSFET and IGBT Fabrication Process with Two Fewer Photomasks  
A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In...
US20100219463 QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE  
A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over...
US20130288441 METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME  
A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor...
US20130032877 N-CHANNEL TRANSISTOR COMPRISING A HIGH-K METAL GATE ELECTRODE STRUCTURE AND A REDUCED SERIES RESISTANCE BY EPITAXIALLY FORMED SEMICONDUCTOR MATERIAL IN THE DRAIN AND SOURCE AREAS  
When forming sophisticated semiconductor devices including high-k metal gate electrode structures and N-channel transistors, superior performance may be achieved by incorporating epitaxially grown...
US20100081243 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
A method for manufacturing a semiconductor device, includes forming a gate oxide film on an SiC region by a first thermal oxidation treatment in a first oxidizing atmosphere, performing a second...
US20130119466 High Voltage Device with Reduced Leakage  
A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a...
US20110156170 INTEGRATED COMMON SOURCE POWER MOSFET DEVICE, AND MANUFACTURING PROCESS THEREOF  
An integrated power MOSFET device formed by a substrate); an epitaxial layer of N type; a sinker region of P type, extending through the epitaxial layer from the top surface and in electrical...
US20100044791 Configurations and methods for manufacturing charge balanced devices  
This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an...
US20090242972 VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and...
US20080217657 Power Semiconductor Device and Method of Manufacturing a Power Semiconductor Device  
A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions...
US20140073100 Methods Of Forming A Vertical Transistor, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells  
Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is...
US20130320431 Vertical Power MOSFET and Methods for Forming the Same  
A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at...
US20090302375 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE METHOD  
A method of manufacturing a semiconductor device includes forming trenches (22), and then selectively etching a buried layer (14) to form a cavity. An insulator is then deposited on the sidewalls...
US20080087942 Vertical channel memory and manufacturing method thereof and operating method using the same  
A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel is protruded from the substrate and has...
US20070264780 Method of fabricating a vertical nano-transistor  
A method of fabricating a vertical nano-transistor by forming holes in a thin metal film to provide the gate region for forming the channel region, applying insulation material to the walls of the...
US20070072352 Insulated gate field effect transistor and manufacturing method thereof  
A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage VDS...
US20140162418 Methods of Forming Vertically-Stacked Structures, and Methods of Forming Vertically-Stacked Memory Cells  
Some embodiments include methods of forming vertically-stacked structures, such as vertically-stacked memory cells. A first hardmask is formed over a stack of alternating electrically conductive...
US20120168861 POWER TRANSISTOR WITH INCREASED AVALANCHE CURRENT AND ENERGY RATING  
A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain...
US20090108339 HIGH VOLTAGE TMOS SEMICONDUCTOR DEVICE WITH LOW GATE CHARGE STRUCTURE AND METHOD OF MAKING  
A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A...
US20140054679 DOPING A NON-PLANAR SEMICONDUCTOR DEVICE  
In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar...
US20120119266 Stressor in Planar Field Effect Transistor Device  
A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a...
US20110300679 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN  
A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor portion overlying the underlying doped...
US20090085111 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
Provided is a semiconductor device and a method of manufacturing a semiconductor device. In the semiconductor device, high-concentration n type impurity regions are formed respectively below gate...
US20090085064 HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD  
A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a...
US20090065856 Semiconductor device having vertical MOS transistor and method for manufacturing the semiconductor device  
In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a...
US20140065778 LOW LOSS SIC MOSFET  
A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the...
US20140054674 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower...
US20130256698 LOW LOSS SIC MOSFET  
A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the...
US20110281411 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
An amorphous silicon layer and a single crystal silicon layer are formed in an upper portion of a silicon pillar. Then, by performing the selective epitaxial growth method twice, an amorphous...
US20100102361 VERTICAL TRANSISTOR AND FABRICATING METHOD THEREOF AND VERTICAL TRANSISTOR ARRAY  
A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar...
US20090179258 NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR DEVICE  
A nitride semiconductor device includes: a nitride semiconductor structure portion including a first layer made of an n-type group III nitride semiconductor, a second layer made of a group III...
US20130256784 MOSFETs with Channels on Nothing and Methods for Forming the Same  
A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed...
US20130020635 Semiconductor device with field threshold MOSFET for high voltage termination  
This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an...