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US20150017771 3D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and...
US20130153978 3D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and...
US20050285175 Vertical SOI Device  
The present invention provides a structure and method of forming vertical transistors. The structure of the present invention comprises: a substrate having an insulator layer formed thereon and a...
US20150072490 VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION  
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions...
US20140264558 FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS  
A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a...
US20140054672 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME  
This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom...
US20120178211 CO-PACKAGING APPROACH FOR POWER CONVERTERS BASED ON PLANAR DEVICES, STRUCTURE AND METHOD  
A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral dif...
US20150069500 VERTICAL TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF  
A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region. The substrate has at least one...
US20140349454 METHODS OF FORMING CHARGE STORAGE STRUCTURES INCLUDING ETCHING DIFFUSED REGIONS TO FORM RECESSES  
Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the recesses. Additional embodiments are...
US20130040429 METHODS OF FORMING CHARGE STORAGE STRUCTURES INCLUDING ETCHING DIFFUSED REGIONS TO FORM RECESSES  
Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the recesses. Additional embodiments are...
US20100151662 FIELD EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD  
The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made...
US20080258209 SEMICONDUCTOR DEVICE AND MANUFATURING METHOD THEREOF  
A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending...
US20090170264 Method of producing semiconductor device  
A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A first conductive type impurity is diffused in the silicon carbide substrate. A...
US20120273884 Superjunction Structures for Power Devices and Methods of Manufacture  
A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second...
US20120273871 Superjunction Structures for Power Devices and Methods of Manufacture  
A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second...
US20090114978 VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME  
A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction...
US20110241104 INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION  
An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel...
US20090159964 VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME  
A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is...
US20090159969 PROCESS FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE COMPRISING CHARGE-BALANCE COLUMN STRUCTURES AND RESPECTIVE DEVICE  
Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the...
US20130005099 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE INCLUDING A DIELECTRIC LAYER  
A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a...
US20110097863 Cross OD FinFET Patterning  
A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask;...
US20140054673 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME  
This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or...
US20130230954 TUNNELING FIELD-EFFECT TRANSISTOR WITH DIRECT TUNNELING FOR ENHANCED TUNNELING CURRENT  
Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons...
US20150140753 Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells  
Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the...
US20140015036 TRENCHED AND IMPLANTED ACCUMULATION MODE METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR  
The present invention provides AccuFETs with single or dual accumulation channels and methods for manufacturing the same. The present invention also provides for products produced by the methods of...
US20110284949 VERTICAL TRANSISTOR AND A METHOD OF FABRICATING THE SAME  
A vertical transistor and a method of fabricating the vertical transistor are provided. The vertical transistor has a substrate, a first electrode formed on the substrate, a first insulation layer...
US20110215377 Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region  
A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode...
US20110073943 TRUE CSP POWER MOSFET BASED ON BOTTOM-SOURCE LDMOS  
A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the...
US20150069330 NANOWIRE FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME  
Provided are a nanowire field-effect transistor and a method for manufacturing the same. The nanowire field-effect transistor can enable a source region to be positioned, with respect to an...
US20120126312 VERTICAL DMOS-FIELD EFFECT TRANSISTOR  
A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET), has a cell structure with a substrate; an epitaxial layer or well of the first conductivity type on the...
US20070048942 Methods of forming field effect transistors on substrates  
The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field...
US20140225185 METHOD OF MAKING A LOW-RDSON VERTICAL POWER MOSFET DEVICE  
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson...
US20130049100 METHOD OF MAKING A LOW-RDSON VERTICAL POWER MOSFET DEVICE  
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson...
US20120126314 VERTICAL DMOS-FIELD EFFECT TRANSISTOR  
A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first...
US20150129886 GALLIUM NITRIDE FIELD EFFECT TRANSISTOR WITH BURIED FIELD PLATE PROTECTED LATERAL CHANNEL  
A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN...
US20090148991 Method of fabricating semiconductor device having vertical channel transistor  
A method of fabricating a semiconductor device having a vertical channel transistor, the method including forming a hard mask pattern on a substrate, forming a preliminary active pillar by etching...
US20080173936 ACCESS DEVICE HAVING VERTICAL CHANNEL AND RELATED SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE ACCESS DEVICE  
An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate...
US20080048245 Semiconductor device and manufacturing methods thereof  
A semiconductor device includes: a substrate having a main surface, a first main electrode formed on the main surface of the substrate, a pillar shaped semiconductor layer formed on the first main...
US20150021621 SELF-ALIGNED GATE BURIED CHANNEL FIELD EFFECT TRANSISTOR  
This disclosure provides a transistor device formed on a wide band gap substrate. The transistor device includes a channel layer and a gate structure physically coupled to the channel layer. The...
US20140256100 ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE  
A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory...
US20140231909 Super Junction Semiconductor Device Comprising Implanted Zones  
In a semiconductor substrate with a first surface and a working surface parallel to the first surface, columnar first and second super junction regions of a first and a second conductivity type are...
US20140021485 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area...
US20140256101 METHODS OF FABRICATING THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES  
A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated...
US20120184077 Configuration and Fabrication of Semiconductor Structure in Which Source and Drain Extensions of Field-effect Transistor Are Defined with Different Dopants  
An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone...
US20080283912 Semiconductor device having super junction structure and method of manufacturing the same  
A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column...
US20130193412 TRANSISTORS AND METHODS OF MANUFACTURING THE SAME  
Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source...
US20090317954 Method for forming vertical channel transistor of semiconductor device  
A method for forming a vertical channel transistor of a semiconductor device includes forming a plurality of pillar patterns over a substrate, forming a gate insulation layer encapsulating the...
US20080179664 SEMICONDUCTOR DEVICE WITH A VERTICAL MOSFET INCLUDING A SUPERLATTICE AND RELATED METHODS  
A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice...
US20100001414 MANUFACTURING A SEMICONDUCTOR DEVICE VIA ETCHING A SEMICONDUCTOR CHIP TO A FIRST LAYER  
A method of manufacturing a semiconductor device. The method includes providing a semiconductor chip including contact elements on a first face and a first layer between the first face and a second...
US20070072416 Method of forming a low resistance semiconductor contact and structure therefor  
In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.