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US20150357445 STRUCTURE AND METHOD FOR VERTICAL TUNNELING FIELD EFFECT TRANSISTOR WITH LEVELED SOURCE AND DRAIN  
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first...
US20150357438 METHOD FOR MANURACTURING PILLAR-SHAPED SEMICONDUCTOR DEVICE  
An N+ region 2a and a P+ region 3a are formed in a Si pillar 6. HfO2 layers 9a and 9c, TiN layers 10b and 10d, and SiO2 layers 11b and 11d are formed to surround the Si pillar 6. Then contact...
US20150357432 SYSTEMS AND METHODS FOR FABRICATING VERTICAL-GATE-ALL-AROUND DEVICES  
Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically...
US20150357413 Three Dimensional NAND Device Having a Wavy Charge Storage Layer  
A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of...
US20150357342 LOW DIELECTRIC CONSTANT INSULATING MATERIAL IN 3D MEMORY  
A memory device includes a plurality of stacks of conductive strips alternating with insulating strips. At least one of the insulating strips includes an insulating material with a dielectric...
US20150349119 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A method for producing a semiconductor device includes a first step of forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped...
US20150349092 TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET  
A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the...
US20150348992 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. The memory...
US20150348991 Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells  
Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the...
US20150348988 SEMICONDUCTOR MEMORY ELEMENT AND PRODUCTION METHOD THEREFOR  
Provided is a semiconductor memory device including a vertical electrode provided on a substrate and a blocking insulating layer provided on a sidewall of the vertical electrode. A plurality of...
US20150348984 METHOD OF MAKING A MONOLITHIC THREE DIMENSIONAL NAND STRING USING A SELECT GATE ETCH STOP LAYER  
A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first...
US20150348848 SELF-ALIGNED NANOWIRE FORMATION USING DOUBLE PATTERNING  
A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to...
US20150348846 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of...
US20150348799 COMPOSITIONS FOR ETCHING  
Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at...
US20150348798 CMP SLURRY COMPOSITION FOR POLISHING AN ORGANIC LAYER AND METHOD OF FORMING A SEMICONDUCTOR DEVICE USING THE SAME  
A chemical mechanical polishing (CMP) slurry composition for polishing an organic layer and a method of forming a semiconductor device using the same are disclosed. The CMP slurry composition may...
US20150340495 VERTICAL COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR ON A GROUP IV SEMICONDUCTOR SUBSTRATE  
Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically...
US20150340374 MEMORY DEVICE  
A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a...
US20150340371 3D INDEPENDENT DOUBLE GATE FLASH MEMORY ON BOUNDED CONDUCTOR LAYER  
A memory device configurable for independent double gate cells, storing multiple bits per cell, includes multilayer stacks of conductive strips configured as word lines. Active pillars are...
US20150340237 Semiconductor Devices with Sharp Gate Edges and Methods to Fabricate Same  
This application discloses semiconductor devices with sharp gate edges including 2D and 3D memory cells, High Electron Mobility Transistors and tri-gate transistors. Implementation of a gate with...
US20150333282 METHODS AND DEVICES FOR SILICON INTEGRATED VERTICALLY ALIGNED FIELD EFFECT TRANSISTORS  
Embodiments of the present disclosure provide for vertically aligned CNTFET, methods of making vertically aligned CNTFET, methods of using vertically aligned CNTFET, and the like.
US20150333174 SEMICONDUCTOR DEVICE WITH TERMINATION STRUCTURE FOR POWER MOSFET APPLICATIONS  
A semiconductor device may have an active device region containing a plurality of active devices and a termination structure that surrounds the active device region. The termination structure...
US20150333170 LATERAL POWER DEVICE HAVING LOW SPECIFIC ON-RESISTANCE AND USING HIGH-DIELECTRIC CONSTANT SOCKET STRUCTURE AND MANUFACTURING METHOD THEREFOR  
Provided is a lateral power device having low specific ON-resistance and using a high-dielectric constant socket structure and a manufacturing method therefor, which relate to semiconductor power...
US20150333153 SEMICONDUCTOR DEVICE HAVING VERTICAL MOSFET WITH SUPER JUNCTION STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME  
A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in...
US20150333152 VERTICAL STRUCTURE AND METHOD OF FORMING THE SAME  
According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure...
US20150333143 Memory Arrays  
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are...
US20150333084 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME  
Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the...
US20150325665 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the...
US20150325654 INTEGRATED ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THEREOF  
An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having...
US20150325642 HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING  
A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The...
US20150325589 Semiconductor Constructions, Methods of Forming Vertical Memory Strings, and Methods of Forming Vertically-Stacked Structures  
Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels....
US20150325585 METHOD FOR FORMING THREE-DIMENSIONAL MEMORY AND PRODUCT THEREOF  
A method for forming a 3D memory is described. A stacked structure including alternately arranged semiconductor layers and insulating layers is formed on a substrate. The stacked structure is...
US20150325582 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality...
US20150325485 Vertical Power MOSFET and Methods of Forming the Same  
A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a...
US20150325444 METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE  
A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating...
US20150318393 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped...
US20150318389 SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the...
US20150318302 METHOD OF FABRICATING A THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE  
A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an...
US20150318300 METHOD OF MAKING DAMASCENE SELECT GATE IN MEMORY DEVICE  
A method of fabricating a memory device includes forming a mask over a top surface of a stack of alternating insulating material layers and control gate electrodes located over a substrate,...
US20150318298 TRENCH VERTICAL NAND AND METHOD OF MAKING THEREOF  
A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer...
US20150318290 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF  
A memory device includes an array of memory cells. At least one of the memory cells includes a plurality of transistors with vertical-gate-all-around configurations and a plurality of active...
US20150318289 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF  
A memory device includes a plurality of memory cells At least one of the memory cells includes a plurality of transistors with vertical-gate-all-around configurations and a plurality of active...
US20150318288 VERTICAL TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL  
Various methods of forming a vertical static random access memory cell and the resulting devices are disclosed. One method includes forming a plurality of pillars of semiconductor material on a...
US20150318214 TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICTAING THE SAME  
The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite...
US20150318213 TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME  
A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the...
US20150311316 VARIABLE RESISTIVE MEMORY DEVICE INCLUDING VERTICAL CHANNEL PMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a...
US20150311211 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (OSC) is formed without using a tilted ion...
US20150311209 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of...
US20150303301 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film formed around the fin-shaped semiconductor layer, a first metal film formed around the first insulating...
US20150303294 VERTICAL SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE VERTICAL SEMICONDUCTOR DEVICE  
Aspects of the invention are directed to a vertical semiconductor device including an element active portion and a voltage withstanding structure portion has a first main electrode and a gate pad...
US20150303184 SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME  
A semiconductor device and a fabrication method for the semiconductor device are provided in which an increase of a forward loss is suppressed and a reverse recovery loss is reduced. A...