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US20160035825 SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a...
US20160035824 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND POWER MODULE  
A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer...
US20160035789 Method Of Manufacturing Semiconductor Device And Semiconductor Device Having Unequal Pitch Vertical Channel Transistors  
A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines....
US20160035742 SPACER PASSIVATION FOR HIGH-ASPECT RATIO OPENING FILM REMOVAL AND CLEANING  
A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening...
US20160035740 NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME  
According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one semiconductor layer extending through the...
US20160035732 THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE  
A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first...
US20160027914 HIGH VOLTAGE TRANSISTOR DEVICE WITH REDUCED CHARACTERISTIC ON RESISTANCE  
Technologies are generally described for reduction of the characteristic on resistance for a transistor device. In some examples, a transistor device may include a source region, a drain region,...
US20160027898 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same  
A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on...
US20160027874 SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type...
US20160027795 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The...
US20160020306 Short-Gate Tunneling Field Effect Transistor Having Non-Uniformly Doped Vertical Channel and Fabrication Method Thereof  
The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect...
US20160020302 METHOD OF SEMICONDUCTOR ARRANGEMENT FORMATION  
Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric...
US20160020206 SEMICONDUCTOR DEVICE INCLUDING A VERTICAL GATE-ALL-AROUND TRANSISTOR AND A PLANAR TRANSISTOR  
A semiconductor device includes a first transistor and a second transistor. Each of the first and second transistors includes a channel. The channel of the first transistor extends in a...
US20160013312 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR  
One semiconductor device includes an element-isolation region formed on a semiconductor substrate, an active region surrounded by said element-isolation region, a semiconductor pillar in the...
US20160013292 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING VERTICAL CHANNEL AND METHOD OF MANUFACTURING THE SAME  
A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. A gate...
US20160013200 NON-VOLATILE MEMORY DEVICE  
According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating...
US20160005811 CHARGE COMPENSATION DEVICE AND MANUFACTURING THEREFOR  
A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel...
US20160005758 THREE-DIMENSIONAL VERTICAL GATE NAND FLASH MEMORY INCLUDING DUAL-POLARITY SOURCE PADS  
A memory includes a three-dimensional array including a plurality of levels is described. Each level includes a bit line pad, a source line pad, and a plurality of strips of semiconductor material...
US20150380555 METHOD AND STRUCTURE FOR STRAINING CARRIER CHANNEL IN VERTICAL GATE ALL-AROUND DEVICE  
Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region (140); a drain region (190) aligned substantially...
US20150380548 VERTICAL DEVICE ARCHITECTURE  
The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation....
US20150380542 Charge Compensation Structure and Manufacturing Therefor  
A charge-compensation semiconductor device includes a semiconductor body including a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor...
US20150380541 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET...
US20150380539 Metal Gate of Gate-All-Around Transistor  
The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a nanowire structure comprising a channel region between a source region and a drain...
US20150380505 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped...
US20150380432 Methods Of Forming A Charge-Retaining Transistor  
A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material...
US20150380430 JUNCTION FORMATION FOR VERTICAL GATE 3D NAND MEMORY  
A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers. An etch process is...
US20150380429 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from the first portion, first channel...
US20150380428 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME  
According to one embodiment, a semiconductor memory device includes a source layer; a stacked body; a columnar section; and a contact section extending in the stacking direction and piercing...
US20150380427 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME  
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a...
US20150380418 THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE AND METHOD OF MAKING THEREOF  
A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends...
US20150372135 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device includes a semiconductor substrate having a first conductivity type, a plurality of pillars extending to a direction perpendicular to a surface of the semiconductor...
US20150372128 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME  
A silicon carbide film includes a first range having a first breakdown voltage holding layer, a charge compensation region, a first junction terminal region, and a first guard ring region. The...
US20150372119 METHOD FOR FABRICATING VERTICALLY STACKED NANOWIRES FOR SEMICONDUCTOR APPLICATIONS  
Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for...
US20150372103 SPLIT GATE POWER SEMICONDUCTOR FIELD EFFECT TRANSISTOR  
The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field...
US20150372087 Semiconductor Switching Devices with Different Local Transconductance  
A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the...
US20150372086 Semiconductor Switching Device with Different Local Threshold Voltage  
A semiconductor device includes a semiconductor substrate having a plurality of switchable cells defining an active area of the semiconductor device, an outer rim, and an edge termination region...
US20150372083 SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET INTERCONNECTING A SOURCE REGION AND A DRAIN REGION  
A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D...
US20150372082 SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET UNIT INTERCONNECTING A SOURCE AND A DRAIN  
A semiconductor device includes a substrate, a first source/drain (S/D), a second S/D, and a semiconductor sheet unit. The substrate extends in a substantially horizontal direction. The first S/D...
US20150372058 METHOD FOR FABRICATING SEMICONDUCTOR APPARATUS  
A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common...
US20150372007 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE  
According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body including a plurality of first layers and a plurality of second layers on a...
US20150372003 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME  
According to one embodiment, a nonvolatile semiconductor memory device, includes: a foundation layer; a stacked body provided on the foundation layer, each of a plurality of first insulating...
US20150364599 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type, and a second semiconductor layer of a second conductivity type...
US20150364577 SEMICONDUCTOR DEVICE MANUFACTURING METHOD  
A method of manufacturing a semiconductor device includes forming a first parallel pn layer; depositing a first-conductivity-type first semiconductor layer on a surface of the first parallel pn...
US20150364572 VERTICAL III-V NANOWIRE FIELD-EFFECT TRANSISTOR USING NANOSPHERE LITHOGRAPHY  
A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel...
US20150364564 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME  
A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a conductive layer, a conductive architecture and a dielectric layer. The...
US20150364488 THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE HAVING A SILICIDE SOURCE LINE AND METHOD OF MAKING THEREOF  
A memory device and a method of making a memory device that includes a stack of alternating layers of a first material and a second material different from the first material over a substrate,...
US20150364381 METHOD OF MANUFACTURING 3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
A method of manufacturing a semiconductor integrated circuit device is provided. The method includes forming a plurality of pillars in a semiconductor substrate, forming an insulating layer...
US20150357462 LDMOS DEVICE AND STRUCTURE FOR BULK FINFET TECHNOLOGY  
A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more...
US20150357461 INTEGRATED TERMINATION FOR MULTIPLE TRENCH FIELD PLATE  
A semiconductor device includes a vertical MOS transistor with a plurality of parallel RESURF drain trenches separated by a constant spacing in a vertical drain drift region. The vertical MOS...
US20150357459 INTEGRATED CHANNEL DIODE  
A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first...