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US20160172369 FORMING MEMORY USING DOPED OXIDE  
A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory...
US20160172366 THREE DIMENSIONAL MEMORY DEVICE WITH BLOCKING DIELECTRIC HAVING ENHANCED PROTECTION AGAINST FLUORINE ATTACK  
Blocking dielectric structures and/or thicker barrier metal films for preventing or reducing fluorine diffusion are provided. A blocking dielectric layer can be formed as an outer layer of a...
US20160172246 NANOWIRE CMOS STRUCTURE AND FORMATION METHODS  
A method includes growing a nanowire from a substrate, forming a sacrificial layer surrounding the nanowire, removing the nanowire from the sacrificial layer to form an opening in the sacrificial...
US20160170304 Methods of forming patterns using photoresist polymers and methods of manufacturing semiconductor devices  
A photoresist polymer includes a first repeating unit and a second repeating unit. The first repeating unit includes a fluorine leaving group that is configured to be removed by a photo-chemical...
US20160163856 VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION  
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions...
US20160163849 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREFOR  
A semiconductor product comprising: a first semiconductor electrode, a second semiconductor electrode and an interconnecting semiconductor electrode defining a third semiconductor electrode; a...
US20160163840 TUNNEL FIELD EFFECT TRANSISTOR (TFET) WITH LATERAL OXIDATION  
A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling...
US20160163817 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE  
The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening...
US20160163804 VERTICAL HIGH-VOLTAGE MOS TRANSISTOR AND METHOD OF FORMING THE MOS TRANSISTOR WITH IMPROVED ON-STATE RESISTANCE  
A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor...
US20160163734 THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME  
A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection...
US20160163731 VERTICAL THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME  
The disclosed technology generally relates to semiconductor devices, and more particularly to a vertical three-dimensional semiconductor device and a method for manufacturing such a device. In one...
US20160163729 THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE  
A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line...
US20160163728 UNIFORM THICKNESS BLOCKING DIELECTRIC PORTIONS IN A THREE-DIMENSIONAL MEMORY STRUCTURE  
A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed...
US20160163602 VERTICAL FIELD EFFECT TRANSISTORS  
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with...
US20160155842 PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME  
An opening extending through a gate insulating layer and a gate conductor layer is formed in the circumferential portion of a Si pillar at an intermediate height of the Si pillar. A laminated...
US20160155734 VERTICAL TRANSISTOR WITH FLASHOVER PROTECTION  
Technologies are generally described for increase of spacing between source and drain regions of a vertical high voltage transistor without a significant corresponding increase in the die size. In...
US20160149049 RUTHENIUM NUCLEATION LAYER FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE  
A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material...
US20160149025 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap...
US20160149020 REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS  
An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact...
US20160149019 Semiconductor Device and Method  
Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped...
US20160149002 MEMORY DEVICE CONTAINING STRESS-TUNABLE CONTROL GATE ELECTRODES  
A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers....
US20160148993 REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS  
An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact...
US20160148945 METAL WORD LINES FOR THREE DIMENSIONAL MEMORY DEVICES  
A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first...
US20160148938 SEMICONDUCTOR DEVICE HAVING A GATE AND A CONDUCTIVE LINE IN A PILLAR PATTERN  
A semiconductor device including a vertical gate and a method for manufacturing the same are disclosed, which prevent a floating body phenomenon, thereby increasing a cell threshold voltage and...
US20160141419 THREE DIMENSIONAL NAND DEVICE HAVING REDUCED WAFER BOWING AND METHOD OF MAKING THEREOF  
A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending...
US20160141408 SUPER JUNCTION FIELD EFFECT TRANSISTOR WITH INTERNAL FLOATING RING  
A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of...
US20160141371 SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME  
In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body...
US20160141294 THREE-DIMENSIONAL MEMORY STRUCTURE WITH MULTI-COMPONENT CONTACT VIA STRUCTURE AND METHOD OF MAKING THEREOF  
A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion...
US20160126311 STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT  
A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first...
US20160126107 ETCHANT COMPOSITIONS FOR NITRIDE LAYERS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME  
An etchant composition for nitride layers includes phosphoric acid in an amount ranging from about 80 weight percent to about 90 weight percent, a silicon-fluorine compound in an amount ranging...
US20160118459 CORNER LAYOUT FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES  
A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell...
US20160118396 THREE DIMENSIONAL NAND DEVICE CONTAINING FLUORINE DOPED LAYER AND METHOD OF MAKING THEREOF  
A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a...
US20160111523 METHOD OF FORMING A VERTICAL DEVICE  
According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the...
US20160111441 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel...
US20160111438 BATCH CONTACTS FOR MULTIPLE ELECTRICALLY CONDUCTIVE LAYERS  
A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one...
US20160111437 THREE-DIMENSIONAL MEMORY STRUCTURE HAVING SELF-ALIGNED DRAIN REGIONS AND METHODS OF MAKING THEREOF  
A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a...
US20160111436 VERTICAL NAND DEVICE CONTAINING PERIPHERAL DEVICES ON EPITAXIAL SEMICONDUCTOR PEDESTAL  
A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack...
US20160111434 THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF  
Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or large grain polycrystalline...
US20160104782 TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
A method of manufacturing a transistor structure includes a step of implanting a light dosage into a substrate at a bit line junction and two cell side junctions, and a step of implanting a light...
US20160104774 NON-PLANAR VERTICAL DUAL SOURCE DRIFT METAL-OXIDE SEMICONDUCTOR (VDSMOS)  
A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure...
US20160104717 APPARATUSES AND METHODS FOR FORMING MULTIPLE DECKS OF MEMORY CELLS  
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials...
US20160099343 TUNNELING FIELD EFFECT TRANSISTOR AND METHODS OF MAKING SUCH A TRANSISTOR  
One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device,...
US20160099254 Memory Hole Structure in Three Dimensional Memory  
In a three dimensional nonvolatile memory, memory holes extend vertically through two or more physical levels in which memory cells are formed. Memory hole structures are formed in memory holes to...
US20160099252 MEMORY HAVING A CONTINUOUS CHANNEL  
The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in...
US20160099250 THREE DIMENSIONAL NAND DEVICE WITH SILICON GERMANIUM HETEROSTRUCTURE CHANNEL  
A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a...
US20160093733 HIGH VOLTAGE MOSFET DEVICES AND METHODS OF MAKING THE DEVICES  
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an...
US20160093732 NON-FLOATING VERTICAL TRANSISTOR STRUCTURE  
A non-floating vertical transistor includes a substrate and a protuberant structure extending from the substrate. A segregating pillar is inside the protuberant structure. A pair of segregated...
US20160093636 Alternating Refractive Index In Charge-Trapping Film In Three-Dimensional Memory  
Techniques are provided for fabricating a three-dimensional, charge-trapping memory device with improved long term data retention. A corresponding three-dimensional, charge-trapping memory device...
US20160093635 VERTICAL MEMORY DEVICE WITH BIT LINE AIR GAP  
A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor...
US20160093611 SEMICONDUCTOR STRUCTURE WITH AN L-SHAPED BOTTOM PLATE  
A semiconductor structure having a first source/drain semiconductor structure connected to a vertical channel such that the source/drain semiconductor structure has a vertical side that is...