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US20140203343 Non-volatile Memory Cell Having A Floating Gate And A Coupling Gate With Improved Coupling Ratio Therebetween  
A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape. An array of such cells...
US20150064864 METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY  
A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to...
US20140367760 METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY  
A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to...
US20090080245 OFFSET NON-VOLATILE STORAGE  
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce...
US20120175696 MULTILAYER FLOATING GATE FIELD-EFFECT TRANSISTOR (FET) DEVICES AND RELATED METHODS  
Multilayer floating gate field-effect transistor (FET) devices and related methods are provided. A multilayer floating gate FET device can include a first floating gate separated via a first...
US20140374812 DEVICE INCLUDING ACTIVE FLOATING GATE REGION AREA THAT IS SMALLER THAN CHANNEL AREA  
A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that...
US20130026553 NVM Bitcell with a Replacement Control Gate and Additional Floating Gate  
Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary...
US20110298034 MEMORY CELL  
A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first channel region (232) and an access...
US20140106525 METHOD OF FORMING PN FLOATING GATE NON-VOLATILE STORAGE ELEMENTS AND TRANSISTOR HAVING N+ GATE  
Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some...
US20100261317 OFFSET NON-VOLATILE STORAGE  
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce...
US20120025289 METAL CONTROL GATE FORMATION IN NON-VOLATILE STORAGE  
Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed...
US20120040504 METHOD FOR INTEGRATING DRAM AND NVM  
The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation...
US20090152645 METHODS FOR ISOLATING PORTIONS OF A LOOP OF PITCH-MULTIPLIED MATERIAL AND RELATED STRUCTURES  
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of...
US20100271878 INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN  
An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon....
US20060275986 Semiconductor intergrated circuit device and process for producing the same  
A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b...
US20080318379 METHOD FOR FABRICATING NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS  
A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as...
US20150093864 NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-LAST METHODOLOGY  
A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in...
US20090147576 FLOATING GATE WITH UNIVERSAL ETCH STOP LAYER  
Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that...
US20130107630 NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIVE COUPLING  
Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate...
US20070190722 METHOD TO FORM UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT  
A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or...
US20120287715 Zero Cost NVM Cell Using High Voltage Devices in Analog Process  
A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate...
US20070287252 Methods of forming variable resistance memory cells, and methods of etching germanium, antimony, and tellurium-comprising materials  
A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching chemistry comprising Cl2 and CH2F2. A...
US20070026605 Fabricating approach for memory device  
To address problems encountered during the fabrication of a nonvolatile memory cell, such as preventing top oxide loss, preventing contact between the nitride and the polysilicon, and reducing the...
US20080291723 SOURCE BIASING OF NOR-TYPE FLASH ARRAY WITH DYNAMICALLY VARIABLE SOURCE RESISTANCE  
A dynamically variable source resistance is provided for each sector of a NOR-type Flash memory device. The variable source resistance of a given sector is set to a relatively low value (i.e.,...
US20090026523 PARTIALLY GATED FINFET  
A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall...
US20080149985 METHOD FOR FABRICATING FLOATING GATES STRUCTURES WITH REDUCED AND MORE UNIFORM FORWARD TUNNELING VOLTAGES  
An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least...
US20060246664 Memory with metal-insulator-metal tunneling program and erase  
The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a...
US20110163356 HYBRID TRANSISTOR  
A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are...
US20130224918 NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL  
A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact...
US20110256679 NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL  
A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact...
US20150214316 SIMPLE AND COST-FREE MTP STRUCTURE  
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate. A floating gate is disposed over a...
US20090001441 Three dimensional quantum dot array  
In one embodiment of the invention, oxidation of silicon in a silicon germanium/silicon lattice may convert a two dimensional array of silicon germanium pillars into a structured three dimensional...
US20080157162 Method of combining floating body cell and logic transistors  
An integrated circuit having both floating body cells and logic devices fabricated in a bulk silicon substrate is described. The floating body cells have electrically floating bodies formed by...
US20150008451 Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell  
A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced...
US20150054049 INTEGRATED SPLIT GATE NON-VOLATILE MEMORY CELL AND LOGIC STRUCTURE  
A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by...
US20140264534 ARCHITECTURE TO IMPROVE CELL SIZE FOR COMPACT ARRAY OF SPLIT GATE FLASH CELL  
Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing...
US20080142868 FLOATING BODY MEMORY AND METHOD OF FABRICATING THE SAME  
A floating body memory includes a semiconductor substrate having a cell region and a peripheral circuit region. A floating body cell is located in the cell region and a first floating body is...
US20070184612 Method for assembling a panel for an LCD  
A method for assembling a liquid crystal display includes providing a thin-film-transistor substrate and a color-filter substrate having an active area and a non-active area, wherein plural...
US20060234449 FLASH GATE STACK NOTCH TO IMPROVE COUPLING RATIO  
A semiconductor flash memory device with increased gate coupling ratio and a method of preparing this flash memory device. The semiconductor flash memory device includes a notched floating...
US20050087793 Embedded non-volatile memory and a method for fabricating the same  
A low density and cost effective embedded non-volatile memory cell includes a semiconductor substrate of a first conductivity type and having device isolation regions and active regions defined...
US20090014769 SUSPENDED-GATE MOS TRANSISTOR WITH NON-VOLATILE OPERATION  
A transistor device with a mobile suspended gate, the device comprising means for piezoelectric actuation of the gate, and a method for producing such a device.
US20090321806 NONVOLATILE MEMORY WITH FLOATING GATES WITH UPWARD PROTRUSIONS  
Substrate isolation regions (570) initially protrude upward above a semiconductor substrate (520) but are later etched down. Before they are etched down, floating gate layer (590) is deposited and...
US20070087503 Improving NROM device characteristics using adjusted gate work function  
A method including adjusting a threshold voltage of an NROM (nitride, read only memory) device by adjusting a work function associated with a gate terminal of the NROM device.
US20110275186 FABRICATING AND OPERATING A MEMORY ARRAY HAVING A MULTI-LEVEL CELL REGION AND A SINGLE-LEVEL CELL REGION  
Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have...
US20150041875 Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate  
A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates (118, 128) on a first substrate area (111) which are encapsulated in one or more...
US20080280409 Memory Arrays, Semiconductor Constructions And Electronic Systems; And Methods Of Forming Memory Arrays, Semiconductor Constructions And Electronic Systems  
Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some...
US20080108193 Cu annealing for improved data retention in flash memory devices  
Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu....
US20070148870 Method for forming common source line in NOR-type flash memory device  
Disclosed is a method for forming a common source line of a NOR-type flash memory. The method includes the steps of forming a photoresist pattern, which is used for exposing a common source area,...
US20080144377 Nonvolatile Semiconductor Storage Unit and Production Method Therefor  
A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers...
US20080212376 METHODS OF OPERATING AND MANUFACTURING LOGIC DEVICE AND SEMICONDUCTOR DEVICE INCLUDING COMPLEMENTARY NONVOLATILE MEMORY DEVICE, AND READING CIRCUIT FOR THE SAME  
Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the...