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US20050136595 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device is provided including the steps of covering the first nitride film formed on the first oxide film within the first region where the first gate...
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US20090127613 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A nonvolatile semiconductor memory device comprises a memory cell array of plural memory cells arranged in matrix. Each memory cell includes a first gate insulator layer formed on a semiconductor...
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US20070018342 |
Devices with nanocrystals and methods of formation
An aspect relates to a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The...
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US20100315884 |
Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof
A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read...
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US20090273013 |
METHOD OF FORMING A SPLIT GATE MEMORY DEVICE AND APPARATUS
A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the...
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US20090050955 |
NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so...
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US20080293197 |
METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
A method of manufacturing a semiconductor memory device includes forming a device separation film on a semiconductor substrate using a mask pattern for defining an entire source line region as an...
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US20080026527 |
AN APPARATUS AND ASSOCIATED METHOD FOR MAKING A FLOATING GATE MEMORY DEVICE WITH INCREASED GATE COUPLING RATIO
A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional...
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US20070252190 |
Nonvolatile memory device and method for manufacturing the same
Provided are a nonvolatile memory device and a method for manufacturing the same. The nonvolatile memory device may include a semiconductor substrate, a floating gate, a second insulation layer, a...
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US20070166903 |
Semiconductor structures formed by stepperless manufacturing
A manufacturing method for an array of polysilicon fins built up into fin blocks that are aligned in a comb-like array occupying a wafer surface. By subsurface and supersurface contact, fin blocks...
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US20060240622 |
Multi-channel semiconductor device and method of manufacturing the same
Provided are a multi-channel semiconductor device and a method for manufacturing the semiconductor device through a simplified process. A sacrificial layer and a channel layer are alternately...
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US20060110882 |
METHODS OF FORMING GATE STRUCTURE AND FLASH MEMORY HAVING THE SAME
A method of forming a gate structure, including forming sequentially a gate dielectric layer, a conductive layer, a protective layer, a sacrificial layer, and a patterned mask layer over a...
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US20120094450 |
MANUFACTURING METHOD OF MULTI-LEVEL CELL NOR FLASH MEMORY
A manufacturing method of a multi-level cell NOR flash memory includes the steps of forming a memory cell area and a peripheral circuit area with the same depth of a shallow trench isolation...
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US20090309152 |
Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory...
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US20080261366 |
NON-VOLATILE MEMORY DEVICE HAVING IMPROVED ERASE EFFICIENCY AND METHOD OF MANUFACTURING THE SAME
A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a...
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US20070296021 |
Nonvolatile semiconductor memory with backing wirings and manufacturing method thereof
A manufacturing method of a nonvolatile semiconductor memory includes steps (a) to (d). The (a) is a step of laminating a 2nd insulating film, a gate film and a hard mask film which cover a 1st...
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US20070138538 |
Method of forming self-aligned floating gate array and flash memory device including self-aligned floating gate array
Disclosed are a flash memory device including a self aligned floating gate array, and a method of forming the self aligned floating gate array for the flash memory device. The flash memory device...
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US20070004140 |
Method of manufacturing a non-volatile semiconductor memory device
In a method of manufacturing a non-volatile semiconductor memory device that includes a first region having a first gate structure and a second region having a second gate structure, the first gate...
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US20090206391 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of...
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US20090026460 |
VERTICAL NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF
A manufacturing method of a vertical non-volatile memory is provided. A first semiconductor layer, a first barrier, a second semiconductor layer, a second barrier and a third semiconductor layer...
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US20080251833 |
Integrated circuits and methods of manufacture
In various embodiments of the invention, integrated circuits and methods of manufacturing integrated circuits are provided. In an embodiment of the invention, an integrated circuit having at least...
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US20080211005 |
SEMICONDUCTOR DEVICE
There is provided a MOSFET-type semiconductor device having a coating insulating film formed to cover the surface portions of MOS transistors formed on a semiconductor substrate. The insulating...
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US20080048241 |
Nonvolatile semiconductor memory device and fabrication method therefor
Disclosed herein is a nonvolatile semiconductor memory device, including a memory transistor. The memory transistor has: a channel formation region defined between two source and drain regions...
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US20080031043 |
Non-volatile memory device
According to an aspect of the present invention, there is provided a semiconductor device including a non-volatile semiconductor memory device, including a memory cell having a electrolyte film, a...
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US20080014700 |
Methods for fabricating improved gate dielectrics
Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide...
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US20070166917 |
Non-volatile memory device and fabricating method therefor
A non-volatile memory device and fabricating method therefor are provided. The non-volatile memory device includes a substrate, a first insulating layer, a conductor layer, a second insulating...
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US20070077707 |
Non volatile memory device and method of manufacturing the same
The present invention provides a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes: a semiconductor substrate including an active region...
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US20070072369 |
NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF
A non-volatile memory includes a substrate, a plurality of isolation layers, a plurality of active layers, a plurality of floating gates, a plurality of control gates and a plurality of doped...
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US20130009231 |
Method for Efficiently Fabricating Memory Cells with Logic FETs and Related Structure
According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common...
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US20110303964 |
NONVOLATILE MEMORY, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
Provided is a nonvolatile memory 10 having a selective gate SG formed below a silicon layer 14, which is to be a channel region formed between a source region S and a drain region D of a...
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US20110101441 |
SELECT GATES FOR MEMORY
Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second...
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US20090230459 |
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A non-volatile semiconductor memory device includes a memory string which is electrically rewritable and includes a plurality of memory cells connected in series. The memory string includes a...
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US20090168529 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD FOR MANUFACTURING THE SAME, AND NONVOLATILE MEMORY ARRAY
A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate....
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US20090127610 |
NON-VOLATILE MEMORY AND THE MANUFACTURING METHOD THEREOF
A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a...
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US20080079059 |
Method of manufacturing a nonvolatile semiconductor memory device and select gate device having a stacked gate structure
A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes...
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US20080076218 |
Memory device and method of manufacturing the same
In a memory device and a method of manufacturing the memory device, a source contact connected to a common source line may be formed on a drain region instead of a source region. A transistor...
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US20080009115 |
Method of manufacturing at least one semiconductor component and memory cells
A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to...
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US20070132005 |
Electrically Erasable and Programmable Read Only Memories Including Variable Width Overlap Regions and Methods of Fabricating the Same
An electrically erasable and programmable read only memory (EEPROM) is fabricated by forming isolation patterns defining active regions in predetermined regions of a semiconductor substrate...
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US20070105312 |
MEMORY CELL WITH NANOCRYSTAL AS DISCRETE STORAGE ELEMENT
A memory cell including: a substrate; a channel region located in the substrate; a tunnel dielectric located over the channel region; and nanocrystals located over the tunnel dielectric.
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US20100093143 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor...
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US20090310425 |
MEMORY DEVICES INCLUDING VERTICAL PILLARS AND METHODS OF MANUFACTURING AND OPERATING THE SAME
In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of...
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US20080099789 |
Self-aligned method of forming a semiconductor memory array of floating gate memory cells with source side erase, and a memory array made thereby
A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type,...
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US20080087933 |
Semiconductor memory device and method of manufacturing the same
Example embodiments relate to a semiconductor memory device including a channel layer pattern on a substrate, the channel layer pattern having a sidewall and an upper face, a spacer on the sidewall...
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US20080079057 |
AGING DEVICE
An aging device includes a semiconductor substrate, an element isolation insulating layer which is formed in a recessed portion of the semiconductor substrate and which has an upper surface higher...
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US20070161188 |
METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
A method of manufacturing a nonvolatile semiconductor memory device includes the steps of preparing a wafer having multiple memory cells, each memory cell having a gate electrode formed on a...
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US20070034955 |
Nonvolatile semiconductor integrated circuit devices and fabrication methods thereof
In a method for manufacturing a semiconductor device, an oxide layer, a first polysilicon layer, and a second polysilicon layer are sequentially provided on a substrate. A first hard mask pattern...
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US20070096204 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin...
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US20070063259 |
Floating-gate memory cell
A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the semiconductor substrate. A...
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US20070048937 |
METHOD OF FABRICATING NON-VOLATILE MEMORY
A method of fabricating a non-volatile memory is provided. A substrate having a memory cell area and a peripheral circuit area is provided. A plurality of device isolation structures is formed in...
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US20060189074 |
STRUCTURE CONTAINING SELF-ALIGNED CONDUCTIVE LINES AND FABRICATING METHOD THEREOF
A method for fabricating self-aligned conductive lines is provided. A substrate with a plurality of isolation structures is provided. The isolation structures are protrusive from the surface of the...
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