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US20080280401 |
INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES
A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a...
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US20080096348 |
CONTACTS FOR SEMICONDUCTOR DEVICES
A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed...
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US20080081410 |
Multi-bit memory technology (MMT) and cells
As the process development has matured and technology has scaled to smaller and smaller dimensions, the Poly-silicon floating gate cell is approaching its scaling limitations, multi-bit storage in...
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