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US20110133310 INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT  
Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to...
US20120040504 METHOD FOR INTEGRATING DRAM AND NVM  
The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation...
US20050153507 Fabrication method for a trench capacitor with an insulation collar  
The present invention provides a fabrication method for a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried...
US20060166433 Recessed collar etch for buried strap window formation without poly2  
A method for manufacturing a trench capacitor with a reduced resistance in a buried strap window for use in a memory circuit such as a dynamic random access memory circuit may be realized by...
US20070090433 Isolation collar void and methods of forming the same  
In a first aspect, a first apparatus is provided. The first apparatus includes a void formed around one or more portions of a microelectronic device in a bulk substrate. The void is adapted to...
US20070105302 Integrated circuit formed on a semiconductor substrate  
An integrated circuit is provided, which is formed on a semiconductor substrate. The integrated circuit comprises electronic elements and isolation elements, wherein the electronic elements and...
US20050054156 CAPACITOR AND FABRICATION METHOD USING ULTRA-HIGH VACUUM CVD OF SILICON NITRIDE  
A method of fabricating a capacitor including an ultra-high vacuum chemical vapor deposition (UHVCVD) step to generate a top-side barrier film layer including silicon nitride at monolayer...
US20100041191 SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE  
A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect...
US20080166842 Etching composition and method for manufacturing a capacitor using the same  
An etching composition for preventing from leaning a capacitor contains hydrofluoric acid (HF), ammonium fluoride (NH4F), an alkyl ammonium fluoride (ReNH3F; where Re is a C1-C10 linear or...
US20070066011 Integrated circuitry production processes, methods, and systems  
The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a substrate. The organic material is...
US20110169131 DEEP TRENCH DECOUPLING CAPACITOR  
Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench...
US20070042542 Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement  
A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first...
US20050014364 Method of suppressing the effect of shining spots present at the edge of a wafer  
Devices formed in a substrate are protected from shining spots present in a periphery of the substrate. A ring of material is formed on the substrate to separate the periphery of the substrate...
US20050221557 Method for producing a deep trench capacitor in a semiconductor substrate  
The present invention provides a method for producing a deep trench capacitor in a semiconductor substrate (1) comprising the steps of: providing a first trench (2) in the semiconductor substrate...
US20080265299 Strained channel dynamic random access memory devices  
DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
US20070093019 Method for producing a connection electrode for two semiconductor zones arranged one above another  
Method for producing a connection electrode for two semiconductor zones arranged one above another The invention relates to a method for producing a connection electrode for a first semiconductor...
US20060234441 Method for preparing a deep trench  
A method for preparing a deep trench first forms a trench in a semiconductor substrate and a stacked structure in the trench, wherein the stacked structure includes at least one...
US20120049262 A DRAM CELL STRUCTURE WITH EXTENDED TRENCH AND A MANUFACTURING METHOD THEREOF  
A DRAM cell structure with extended trench, the DRAM cell structure comprises: a NMOS transistor and a trench capacitor connected with the source electrode of the NMOS transistor; the trench...
US20050205917 Trench capacitor having an insulation collar and corresponding fabrication method  
The present invention provides a trench capacitor, in particular for use in a semiconductor memory cell, having a trench (5) formed in a semiconductor substrate (1); an insulation collar (3) in...
US20050054158 BULK CONTACT MASK PROCESS  
In vertical transistor trench DRAM arrays, the problem of pinching off the transistor bodies in the P-well is addressed by etching a set of trenches between the DRAM cell trenches down to a level...
US20050260812 Memory cell having a trench capacitor and method for fabricating a memory cell and trench capacitor  
A memory cell having a trench capacitor, a trench capacitor, and a method is disclosed. In one embodiment, the method for fabricating a trench capacitor with a first capacitor electrode, a first...
US20070264771 Dual work function recessed access device and methods of forming  
A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed...
US20090250738 SIMULTANEOUS BURIED STRAP AND BURIED CONTACT VIA FORMATION FOR SOI DEEP TRENCH CAPACITOR  
A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried...
US20050245025 Method of fabricating bottle trench capacitors using an electrochemical etch with electrochemical etch stop  
A method of forming trench capacitors in, e. g., a DRAM device, using an electrochemical etch with built-in etch stop to fabricate well-defined bottle-shaped capacitors is described. The process...
US20140220749 A VERTICAL MOSFET TRANSISTOR WITH A VERTICAL CAPACITOR REGION  
Consistent with an example embodiment, a method of may be provided to manufacture a vertical capacitor region that comprises a plurality of said trenches, wherein the portions of the semiconductor...
US20120302020 SOI Trench Dram Structure With Backside Strap  
In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a...
US20070004129 SEMICONDUCTOR DEVICE HAVING FINFET AND METHOD OF FABRICATING THE SAME  
In one embodiment, a semiconductor device includes a plurality of fin-shaped active regions defined by a trench formed in a substrate with a predetermined depth; an isolation layer formed inside...
US20080057660 Step-gate for a semiconductor device  
A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source/drain region located within the recessed...
US20090166701 One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell  
In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first...
US20120025288 SOI Trench DRAM Structure With Backside Strap  
In one exemplary embodiment, a semiconductor structure including: a silicon-on-insulator substrate having of a top silicon layer overlying an insulation layer, where the insulation layer overlies...
US20070161180 Automatic layer deposition process  
The atomic layer deposition process according to the invention provides the following steps for the production of homogeneous layers on a substrate. The substrate is introduced into a reaction...
US20070099372 Device having active regions of different depths  
An SOI device having SOI layers at two or more different depths below the surface of active regions of the device. Transistors for high-speed digital applications may be formed in the shallower...
US20070026602 METHOD OF MINIMAL WAFER SUPPORT ON BEVEL EDGE OF WAFER  
The present invention generally provides a method and apparatus for supporting and transferring a substrate in and out a wet cleaning chamber with minimal contact. One embodiment of the present...
US20090224304 SOFT ERROR PROTECTION STRUCTURE EMPLOYING A DEEP TRENCH  
A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower...
US20050090073 MOS transistor having improved total radiation-induced leakage current  
A shallow-trench isolation includes a semiconductor substrate. Spaced apart source and drain regions define an active region in the semiconductor substrate. A single isolation trench is in the...
US20080185680 STRUCTURE AND METHOD FOR MAKING ON-CHIP CAPACITORS WITH VARIOUS CAPACITANCES  
A method for manufacturing a device includes forming trenches of different morphologies into a substrate. At the upper surfaces, the trenches have different orientations with respect to each...
US20090256185 METALLIZED CONDUCTIVE STRAP SPACER FOR SOI DEEP TRENCH CAPACITOR  
A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate....
US20100032742 INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT AND METHODS OF MAKING  
A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor...
US20100252873 TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE  
Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device...
US20080102577 Method for Preparing a Trench Capacitor Structure  
A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a buried bottom electrode on the lower outer surface of the trench. A dielectric layer...
US20100052026 DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY  
A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer,...
US20060141701 Semiconductor device having trench capacitors and method for making the trench capacitors  
A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench...
US20070246763 TRENCH STEP CHANNEL CELL TRANSISTOR AND MANUFACTURE METHOD THEREOF  
A trench step channel cell transistor and a manufacture method thereof are disclosed. The transistor could be applied to increase the channel length thereof. The transistor comprises a step...
US20140065777 DRAM WITH DUAL LEVEL WORD LINES  
A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a...
US20140021523 DRAM WITH DUAL LEVEL WORD LINES  
A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a...
US20070037346 Rapid thermal annealing of targeted thin film layers  
A method for rapid thermal annealing of thin film layers is provided. The method directs a series of pulses or flashes of heat energy toward a targeted layer on a substrate. Each pulse may be at a...
US20150249089 Memory Cells and Methods Of Forming Memory Cells  
A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a...
US20130087840 Memory Cells And Methods Of Forming Memory Cells  
A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a...
US20060141700 Method for fabricating semiconductor memory device having recessed storage node contact plug  
A semiconductor memory device and a method for fabricating a semiconductor memory device are provided. The method includes forming an inter-layer insulation layer having a storage node contact...
US20070004127 Method of fabricating a transistor having the round corner recess channel structure  
In fabricating a transistor having the round corner recess channel structure, a buffer layer and a hard mask layer are formed in the active area of a semiconductor substrate. The buffer layer and...

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