|
Match
|
Document |
Document Title |
|
|
US20090311838 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a...
|
|
|
US20090294870 |
Semiconductor device with trench gate and method of manufacturing the same
A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate...
|
|
|
US20090283840 |
METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR
A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least...
|
|
|
US20090242960 |
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and having a stacked gate structure formed by sequentially stacking a tunnel...
|
|
|
US20090242944 |
METHOD OF FORMING A SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION
A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress...
|
|
|
US20090246930 |
METAL CAPACITOR INCLUDING LOWER METAL ELECTRODE HAVING HEMISPHERICAL METAL GRAINS
Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains...
|
|
|
US20090236669 |
METAL GATE TRANSISTOR AND POLYSILICON RESISTOR AND METHOD FOR FABRICATING THE SAME
A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then...
|
|
|
US20090231899 |
PHASE CHANGE RANDOM ACCESS MEMORY AND LAYOUT METHOD OF THE SAME
A phase change random access memory (PRAM) includes a cell array divided into an active region and a dummy active region. A bitline is formed across the active region and the dummy active region...
|
|
|
US20090224331 |
SEMICONDUCTOR STORAGE DEVICE USING MAGNETORESISTIVE EFFECT ELEMENT AND METHOD OF MANUFACTURING THE SAME
A semiconductor storage device includes a semiconductor substrate, a source region, a source line, and a bit line. The source region is formed in an element region formed on the semiconductor...
|
|
|
US20090221115 |
REDUCTION OF MEMORY INSTABILITY BY LOCAL ADAPTATION OF RE-CRYSTALLIZATION CONDITIONS IN A CACHE AREA OF A SEMICONDUCTOR DEVICE
By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the...
|
|
|
US20090221117 |
INTEGRATED CIRCUIT SYSTEM EMPLOYING RESISTANCE ALTERING TECHNIQUES
An integrated circuit system that includes: providing a substrate including a first region and a second region; forming a first device over the first region and a resistance device over the second...
|
|
|
US20090212843 |
SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD
A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting...
|
|
|
US20090189136 |
SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a...
|
|
|
US20090124029 |
METHOD OF FABRICATING RESISTOR AND PROXIMATE DRIVE TRANSISTOR FOR A PRINTHEAD
A method of fabricating a resistor-drive transistor architecture for a printhead of a printer, by depositing printer communication and drive electronics on the printhead. The drive electronics are...
|
|
|
US20090101990 |
Simiconductor integrated circuit device and method of manufacturing the same
A semiconductor integrated circuit device includes a first dopant region in a semiconductor substrate, an isolation region on the semiconductor substrate, the isolation region surrounding the first...
|
|
|
US20090098696 |
Fabrication Process of a Semiconductor Device Having a Capacitor
A method of manufacturing a semiconductor device includes forming a first trench in a capacitor device region of a semiconductor substrate, forming a capacitor insulation film over a sidewall...
|
|
|
US20090093096 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are...
|
|
|
US20090045472 |
Methodology for Reducing Post Burn-In Vmin Drift
A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm −3 . A gate dielectric is located over the substrate...
|
|
|
US20090027822 |
Transient blocking unit having a fab-adjustable threshold current
A transient blocking unit (TBU) is a transistor circuit that is normally on, but rapidly and automatically switches to a high-resistance current blocking state when a current threshold is exceeded,...
|
|
|
US20090020828 |
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
A first MIS transistor includes a first source/drain region formed outside a first sidewall spacer in a first active region, a first silicide film formed on the first source/drain region, and a...
|
|
|
US20090003082 |
Method of making memory cell with voltage modulated sidewall poly resistor
A method of making a two terminal nonvolatile memory cell includes forming a first electrode, forming a charge storage medium, forming a resistive element, and forming a second electrode. The...
|
|
|
US20080310209 |
Circuit, biasing scheme and fabrication method for diode accesed cross-point resistive memory array
Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass...
|
|
|
US20080286921 |
METHODS OF FORMING SILICIDES OF DIFFERENT THICKNESSES ON DIFFERENT STRUCTURES
The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or...
|
|
|
US20080272457 |
Formation Of Dummy Features And Inductors In Semiconductor Fabrication
A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate...
|
|
|
US20080258232 |
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
A semiconductor device includes a substrate, an insulating film disposed on the substrate, a resistor groove disposed in the insulating film, and a resistor disposed in the resistor groove. The...
|
|
|
US20080211019 |
FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING A FIELD-EFFECT TRANSISTOR
A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein...
|
|
|
US20080211028 |
ELECTRO-STATIC DISCHARGE PROTECTION DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING ELECTRO-STATIC DISCHARGE PROTECTION DEVICE
An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the...
|
|
|
US20080185652 |
Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors
Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells....
|
|
|
US20080182373 |
Method for Integrally Forming an Electrical Fuse Device and a MOS Transistor
A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on...
|
|
|
US20080169515 |
SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME
Semiconductor devices are disclose that include a first doped region and a second doped region spaced apart from each other and defined within a same well of a semiconductor substrate. A gate...
|
|
|
US20080160686 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
A semiconductor device includes a semiconductor substrate, a field effect transistor (FET), contact plugs, a resistive element (specific member) and interconnects. Contact plugs are connected to...
|
|
|
US20080149913 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device is disclosed, which includes a first memory cell array formed on a semiconductor substrate and composed of a plurality of memory cells stacked in layers each having a...
|
|
|
US20080135825 |
PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
Provided are a phase-change memory device and a method of fabricating the same. The phase-change memory device includes a transistor disposed on a semiconductor substrate and including a gate...
|
|
|
US20080099836 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
A trench is formed so as to reach a p − -type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is...
|
|
|
US20080096344 |
Method for Manufacturing a Resistor Random Access Memory with a Self-Aligned Air Gap insulator
A method for manufacturing a resistor random access memory with a self-aligned air gap insulator. A high density plasma deposition on the stack of post-patterned layers produces a hard mask that is...
|
|
|
US20080093706 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor device that solves the problem of a conventional semiconductor device. In the conventional semiconductor device, a resistor is connected with a wiring layer via a...
|
|
|
US20080096341 |
Method for Manufacturing a Resistor Random Access Memory with Reduced Active Area and Reduced Contact Areas
A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the...
|
|
|
US20080079081 |
Semiconductor apparatus and manufacturing method
A semiconductor apparatus comprises a cell section including at least two transistors. A layer interval insulation coat is formed at least overlying the gate electrode use polysilicon and the gate...
|
|
|
US20080068047 |
Semiconductor device and production method of the same
A disclosed method of producing a semiconductor device includes the steps of (A) forming a gate electrode and a trimming fuse on a semiconductor substrate; (B) forming a side wall insulating film...
|
|
|
US20080061349 |
NONVOLATILE SEMICONDUCTOR MEMORY WITH RESISTANCE ELEMENTS AND METHOD OF MANUFACTURING THE SAME
A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell...
|
|
|
US20080064161 |
MEMORY CELL HAVING BAR-SHAPED STORAGE NODE CONTACT PLUGS AND METHODS OF FABRICATING SAME
According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line...
|
|
|
US20080057639 |
Semiconductor constructions, and methods of forming semiconductor constructions and flash memory cells
Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in...
|
|
|
US20080057640 |
METHOD FOR FABRICATING FIRST ELECTRODE OF CAPACITOR
A method for fabricating a first electrode of a capacitor is described. A substrate comprising an insulating layer formed thereon is provided. The insulating layer has an opening. A silicon layer...
|
|
|
US20080050871 |
Methods for removing material from one layer of a semiconductor device structure while protecting another material layer and corresponding semiconductor device structures
Methods for removing material from one layer of a semiconductor device structure, such as an etch stop layer beneath a capacitor container, without substantially removing material from an overlying...
|
|
|
US20080050872 |
Fabrication of a high speed RRAM having narrow pulse width programming capabilities
A method of selecting a cathode material and a resistance material for use in a RRAM includes determining the work function of a group of potential resistance materials; determining the work...
|
|
|
US20080048228 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A...
|
|
|
US20080044970 |
Memory structure and method for preparing the same
A memory structure comprises a semiconductor substrate, an active are positioned in the semiconductor substrate, a plurality of doped regions positioned in the semiconductor substrate, a first...
|
|
|
US20080032470 |
METHOD FOR FABRICATING NON-VOLATILE MEMORY
|
|
|
US20080026525 |
Semiconductor processing method and chemical mechanical polishing methods
This invention includes a chemical mechanical polishing method including providing a substrate having an organic material to be polished by chemical mechanical polishing. In one implementation, the...
|
|
|
US20080014693 |
SILICON CARBIDE VERTICAL MOSFET DESIGN FOR FAST SWITCHING APPLICATIONS
A vertical MOSFET device includes a well region of a first conductivity type formed within a surface of a substrate of a second conductivity type opposite the first conductivity type. A doped...
|