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US20150187938 LOW COST DEMOS TRANSISTOR WITH IMPROVED CHC IMMUNITY  
An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance...
US20100308415 ANALOGUE THIN-OXIDE MOSFET  
A dual gate oxide CMOS technology providing three types of transistor; a thin oxide device, a thick oxide device, and a thin oxide device using the implant type of the thick oxide device for...
US20130288439 Zener Diode Structure and Process  
A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last...
US20130082330 Zener Diode Structure and Process  
A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last...
US20140319616 METHOD FOR PRODUCING A METAL-GATE MOS TRANSISTOR, IN PARTICULAR A PMOS TRANSISTOR, AND CORRESPONDING INTEGRATED CIRCUIT  
At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation...
US20090108364 DUAL WORKFUNCTION SILICIDE DIODE  
A CMOS diode and method of making it are disclosed. In one embodiment, the diode comprises a silicon substrate having an N doped region and a P doped region. A first silicide region is formed on...
US20150171104 COMPLEMENTARY SONOS INTEGRATION INTO CMOS FLOW  
Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a...
US20100327335 METHOD OF BUILDING COMPENSATED ISOLATED P-WELL DEVICES  
Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly...
US20050026346 Device for the manipulation of limited quantities of liquids  
Device for manipulation of limited quantities of liquids with the following features: the device has at least one solid; the solid has surface areas in which different capillary forces act; one or...
US20140087531 Two Step Poly Etch LDMOS Gate Formation  
A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the...
US20150140748 INTEGRATED CIRCUIT STRUCTURE TO RESOLVE DEEP-WELL PLASMA CHARGING PROBLEM AND METHOD OF FORMING THE SAME  
A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the...
US20150194439 Embedded NVM in a HKMG Process  
A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213)...
US20110039378 METHOD OF FABRICATING ESD DEVICES USING MOSFET AND LDMOS ION IMPLANTATIONS  
A method of forming complementary metal-oxide-silicon logic field effect transistors, high power transistors and electrostatic discharge protection diodes and/or electrostatic discharge protection...
US20050186754 Solid-state imaging apparatus having multiple anti-reflective layers and method for fabricating the multiple anti-reflective layers  
A solid-state imaging apparatus comprising multiple anti-reflective layers which can improve a smear characteristic while suppressing a dark defect and a method for fabricating the multiple...
US20100032748 CMOS Thermoelectric Refrigerator  
A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less...
US20050085028 Method and structure to suppress external latch-up  
A method and structure for protection against latch-up is provided. Integrated circuits manufactured in accordance with the present disclosure feature well and substrate contacts of varying...
US20130328124 GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL  
A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate...
US20080290418 Method for Integrating Nanotube Devices with CMOS for RF/Analog SoC Applications  
A method is provided of integrating the formation of nanotube devices on the same substrate or wafer as CMOS devices in a standard CMOS process. During a CMOS formation process, a region of the...
US20090242949 CMOS IMAGE SENSOR WITH REDUCED DARK CURRENT  
A carbon-containing semiconductor layer is formed on exposed surfaces of a p-doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the...
US20090098694 CD GATE BIAS REDUCTION AND DIFFERENTIAL N+ POLY DOPING FOR CMOS CIRCUITS  
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a...
US20100173458 LATERAL DOUBLE DIFFUSED MOSFET TRANSISTOR WITH A LIGHTLY DOPED SOURCE  
Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible...
US20050079663 Method of forming a composite  
The invention relates to a method of forming a composite, to composites and devices produced by said method, and to uses thereof.
US20050074934 Electrodeposited layer  
A thin layer of precious metal that is electroplated through a mask onto a conductive substrate, as to form gold plated contacts, is formed with numerous microscopic recesses to produce a...
US20050003600 Gas treating device and gas treating method  
A gas processing apparatus 1 includes a processing container 2 for applying a processing to a wafer W while using a processing gas, a mount table 5 arranged in the processing container 2 to mount...
US20140206160 Method of Forming A Gated Diode Structure for Eliminating RIE Damage From Cap Removal  
A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of...
US20110156157 ONE-TIME PROGRAMMABLE CHARGE-TRAPPING NON-VOLATILE MEMORY DEVICE  
A one-time programmable (OTP) charge-trapping non-volatile memory (NVM) device is described. In an embodiment, an OTP transistor is formed using a thick gate oxide typically used in producing an...
US20050048724 Deep submicron manufacturing method for electrostatic discharge protection devices  
The present invention provides a manufacturing method of an electrostatic discharge protection device for deep submicron manufacturing processing. In deep submicron manufacturing processing,...
US20090302394 CMOS INTEGRATED CIRCUITS WITH BONDED LAYERS CONTAINING FUNCTIONAL ELECTRONIC DEVICES  
A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric...
US20130313651 INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES  
An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode...
US20050042812 Method for manufacturing differential isolation structures in a semiconductor electronic device and corresponding structure  
Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method...
US20050245018 Optoelectronic component  
Optoelectronic component, having a housing body (2), an optoelectronic semiconductor chip (3) arranged in a recess (6) of the housing body, and having electrical terminals (1A, 1B), the...
US20120115292 METHOD FOR INTEGRATING SONOS NON-VOLATILE MEMORY INTO A STANDARD CMOS FOUNDRY PROCESS FLOW  
An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a conventional complementary metal oxide semiconductor (CMOS)...
US20080293196 Method for fabricating multi-resistive state memory devices  
A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal...
US20080061373 SYSTEM-IN-PACKAGE TYPE STATIC RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHOD THEREOF  
A device may include at least one of the following: A first substrate including a plurality of N-channel metal oxide semiconductor transistors, with the N-channel MOS transistors including an...
US20050186723 Methods and apparatuses for heat treatment of semiconductor films upon thermally susceptible non-conducting substrates  
In a method for crystallization or dopant activation heat treatment of a semiconductor film upon a thermally susceptible non-conducting substrate lying onto a susceptor, an induction coil is...
US20120320480 DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT CHIP AGAINST ATTACKS  
An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each...
US20050221552 Substrate support for in-situ dry clean chamber for front end of line fabrication  
A substrate support assembly and method for supporting a substrate are provided. In at least one embodiment, the support assembly includes a body having one or more fluid conduits disposed...
US20090057770 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device capable of preventing malfunction of a Schottky diode to reduce a failure ratio of the semiconductor device and a method for fabricating the same are disclosed. The...
US20050208716 Semiconductor integrated circuit device and production method thereof  
A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a...
US20080227249 CMOS Image Sensor White Pixel Performance  
Methods and systems for forming a photodiode in a substrate, forming a source/drain region in the substrate and extending over at least a portion of the photodiode, and growing a thermal oxide...
US20150035072 METHODS AND APPARATUSES FOR FORMING MULTIPLE RADIO FREQUENCY (RF) COMPONENTS ASSOCIATED WITH DIFFERENT RF BANDS ON A CHIP  
A method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second...
US20140273366 Semiconductor Devices and Methods of Manufacture Thereof  
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type...
US20140367791 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an...
US20060057799 Substrate processing apparatus  
A substrate processing apparatus stably and efficiently conducts a film forming process on a substrate to be processed. In the substrate processing apparatus, the substrate to be processed is...
US20140335669 EMBEDDED NON-VOLATILE MEMORY  
The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an...
US20100264496 SRAM MEMORY CELL PROVIDED WITH TRANSISTORS HAVING A VERTICAL MULTICHANNEL STRUCTURE  
A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel...
US20100015745 METHOD AND STRUCTURE FOR A CMOS IMAGE SENSOR USING A TRIPLE GATE PROCESS  
A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method form a first...
US20090061578 Method of Manufacturing a Semiconductor Microstructure  
A method of manufacturing a semiconductor microstructure comprises: forming a standard CMOS wafer with at least one micro-electro-mechanical structure on a top surface of a silicon substrate,...
US20080017906 SOI DEVICE AND METHOD FOR ITS FABRICATION  
A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline...
US20100163942 CMOS IMAGE SENSOR HAVING DOUBLE GATE INSULATOR THEREIN AND METHOD FOR MANUFACTURING THE SAME  
A method for manufacturing a CMOS image sensor includes: preparing a semiconductor substrate incorporating therein a p-type epitaxial layer by epitaxially growing up an upper portion of the...

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