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US20120315733 METHOD OF FABRICATING GATE ELCTRODE USING A TREATED HARD MASK  
A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet...
US20140120668 STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER  
A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates...
US20120190158 NMOS TRANSISTOR WITH ENHANCED STRESS GATE  
A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type...
US20110248349 Vertical Stacking of Field Effect Transistor Structures for Logic Gates  
Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in...
US20130320449 LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS  
A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side...
US20130087856 Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate  
A CMOS structure is formed on a semiconductor substrate that includes first and second regions having an nFET and a pFET respectively formed thereon. Each nFET and pFET device is provided with a...
US20110195548 METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK  
A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard...
US20120001266 GATE STRUCTURES AND METHOD OF FABRICATING SAME  
A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the...
US20080230841 INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER  
An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer;...
US20140048887 INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY  
An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a...
US20140003133 SRAM LAYOUTS  
Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a...
US20120282744 Reduced Threshold Voltage-Width Dependency and Reduced Surface Topography in Transistors Comprising High-K Metal Gate Electrode Structures by a Late Carbon Incorporation  
Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate...
US20110108922 INTEGRATED CIRCUITS INCLUDING METAL GATES AND FABRICATION METHODS THEREOF  
A method of forming an integrated circuit is provided. The method includes forming a gate electrode of an NMOS transistor over a substrate by a gate-first process. A gate electrode of a PMOS...
US20050275034 A MANUFACTURABLE METHOD AND STRUCTURE FOR DOUBLE SPACER CMOS WITH OPTIMIZED NFET/PFET PERFORMANCE  
Disclosed is a method and structure where a first spacer is formed and an NFET is implanted, and then a second spacer is formed and a PFET is implanted. A dry nitride etch is then performed which...
US20130107610 SRAM CELL WITH INDIVIDUAL ELECTRICAL DEVICE THRESHOLD CONTROL  
A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of...
US20110133189 NMOS ARCHITECTURE INVOLVING EPITAXIALLY-GROWN IN-SITU N-TYPE-DOPED EMBEDDED eSiGe:C SOURCE/DRAIN TARGETING  
An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a...
US20130149821 Methods for a Gate Replacement Process  
A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the...
US20090224326 AVOIDING PLASMA CHARGING IN INTEGRATED CIRCUITS  
A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness...
US20130009251 OFFSET SCREEN FOR SHALLOW SOURCE/DRAIN EXTENSION IMPLANTS, AND PROCESSES AND INTEGRATED CIRCUITS  
A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a...
US20140342514 METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH THE IMPLANTATION OF NITROGEN  
A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region,...
US20080164531 Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack  
A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the...
US20100164002 DUAL SALICIDE INTEGRATION FOR SALICIDE THROUGH TRENCH CONTACTS AND STRUCTURES FORMED THEREBY  
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming an NMOS silicide on an NMOS source/drain contact area, forming a first...
US20150187768 POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE IN DUAL STRESS LINER PROCESS FLOW  
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate...
US20070262385 SELECTIVE UNIAXIAL STRESS RELAXATION BY LAYOUT OPTIMIZATION IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT  
An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained...
US20120119301 METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOUNDARY  
An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method...
US20130032890 SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES  
CMOS devices (60, 61, 61′) having improved latch-up robustness are provided by including with one or both WELL regions (22, 29) underlying the source-drains (24, 25; 31, 32) and the body contacts...
US20150170962 METAL ON ELONGATED CONTACTS  
An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to...
US20090101983 Method of Achieving Dense-Pitch Interconnect Patterning in Integrated Circuits  
Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum...
US20070066002 Source capacitor enhancement for improved dynamic IR drop prevention  
An implant is added at the interface between the source region of an MOS transistor and the well material to improve dynamic IR drop performance. The additional implant raises the underlying...
US20130228868 ELECTROSTATIC DISCHARGE PROTECTION DEVICES  
A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain...
US20080315317 SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS  
A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the...
US20120126197 Structure and process of basic complementary logic gate made by junctionless transistors  
The present invention discloses a structure and process of basic complementary logic gate made by junctionless transistors. Junctionless N-channel transistor(s) and junctionless P-channel...
US20070178634 CMOS SEMICONDUCTOR DEVICES HAVING DUAL WORK FUNCTION METAL GATE STACKS  
CMOS semiconductor devices having dual work function metal gate structures that are formed using fabrication techniques that enable independent work function control for PMOS and NMOS device and...
US20060223254 Display panel drive device  
A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by...
US20140375367 PSEUDO-CML LATCH AND DIVIDER HAVING REDUCED CHARGE SHARING BETWEEN OUTPUT NODES  
In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel...
US20140264380 Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material  
A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face...
US20100308413 3-D SINGLE GATE INVERTER  
A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect...
US20110169096 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS  
An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor...
US20060252191 Methodology for deposition of doped SEG for raised source/drain regions  
A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source...
US20090152624 INTEGRATED CIRCUIT DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT DEVICE  
An integrated circuit device with a semiconductor body and a method for the production of a semiconductor device a provided. The semiconductor body comprises a cell field with a drift zone of a...
US20070132032 Selective stress relaxation of contact etch stop layer through layout design  
A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The...
US20140210012 Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions  
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a...
US20050118758 Method for arranging layout of CMOS device  
A method for arranging a layout of a CMOS (Complementary Metal-Oxide Semiconductor) device is provided. The current direction of the N-type MOS device is perpendicular to the P-type MOS device....
US20090152639 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement  
Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the...
US20070257310 Body-tied MOSFET device with strained active area  
A body-tied MOSFET device and method of fabrication are presented. In the method of fabrication, oxygen diffuses and reacts down a first axis of a pFET or nFET. This results in a partial oxidation...
US20060263961 Method for Forming Dual Fully Silicided Gates and Devices with Dual Fully Silicided Gates  
A method for manufacturing CMOS devices with fully silicided (FUSI) gates is described. A metallic gate electrode of an NMOS transistor and a metallic gate electrode of a pMOS transistor have a...
US20120267683 EARLY EMBEDDED SILICON GERMANIUM WITH INSITU BORON DOPING AND OXIDE/NITRIDE PROXIMITY SPACER  
Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the...
US20070164367 CMOS gates with solid-solution alloy tunable work functions  
Gates of at least one of NMOS transistors and PMOS transistors of a CMOS integrated circuit are formed with a solid-solution alloy of at least two metals. The work function of the gate electrode...
US20140239415 STRESS MEMORIZATION IN RMG FINFETS  
Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate...
US20130273702 Integration Flow For LDD And Spacer Fabrication On A Sacrificial Amorphous Carbon Gate Structure  
An integration flow for LDD and spacer fabrication on a sacrificial amorphous carbon gate structure, form first spacer by way of depositing on the si substrate which have gate structure first....