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US20090302390 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH DIFFERENT METALLIC GATES  
A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor cap ( 26 ) is formed over gate dielectric ( 24 ) and patterned to be present in a...
US20090305474 STRAINED-SILICON CMOS DEVICE AND METHOD  
The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain...
US20090298244 Mobility Enhanced FET Devices  
NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state...
US20090294868 DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY INDUCING DIFFERENT LATERAL STRAIN LEVELS IN THE ACTIVE REGION  
The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of a strain-inducing mechanism, such as a stressed...
US20090294801 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE  
Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including...
US20090289379 Methods of Manufacturing Semiconductor Devices and Structures Thereof  
Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region...
US20090289300 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME  
First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r 1 ′ of the upper corner...
US20090283829 FINFET WITH A V-SHAPED CHANNEL  
A fin-type field effect transistor (finFET) structure comprises a substrate having a planar upper surface, an elongated fin on the planar upper surface of the substrate (wherein the length and the...
US20090283835 METHOD FOR FABRICATING A DUAL WORKFUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF  
A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region...
US20090283837 Semiconductor Devices and Methods of Manufacture Thereof  
Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor...
US20090278180 CMOS IMAGE SENSOR WITH ASYMMETRIC WELL STRUCTURE OF SOURCE FOLLOWER  
Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having...
US20090280645 Method of fabricating semiconductor device  
Provided is a method of fabricating a semiconductor device including a dual suicide process. The method may include sequentially siliciding and stressing a first MOS region, and sequentially...
US20090267160 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device comprises an anti-fuse element. The anti-fuse element includes a semiconductor substrate, a first gate insulating film, a first gate electrode, a high-concentration impurity...
US20090263944 Method for making low Vt gate-first light-reflective-layer covered dual metal-gates on high-k CMOSFETs  
This invention proposes a method for making low V t light-reflective-layer/dual-metal-gates/high-κ CMOSFETs with simple light-irradiation anneal and light-reflective-layer covered dual...
US20090230475 FIELD EFFECT STRUCTURE INCLUDING CARBON ALLOYED CHANNEL REGION AND SOURCE/DRAIN REGION NOT CARBON ALLOYED  
A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device structure. The field effect device structure includes a gate electrode located over...
US20090224302 SEMICONDUCTOR DEVICE WITH INHERENT CAPACITANCES AND METHOD FOR ITS PRODUCTION  
A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In...
US20090224326 AVOIDING PLASMA CHARGING IN INTEGRATED CIRCUITS  
A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness...
US20090227078 CMOS Devices having Dual High-Mobility Channels  
A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor...
US20090221115 REDUCTION OF MEMORY INSTABILITY BY LOCAL ADAPTATION OF RE-CRYSTALLIZATION CONDITIONS IN A CACHE AREA OF A SEMICONDUCTOR DEVICE  
By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the...
US20090218633 CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS  
A recessed transistor configuration may be provided selectively for one type of transistor, such as N-channel transistors, thereby enhancing strain-inducing efficiency and series resistance, while...
US20090218631 SRAM CELL HAVING ASYMMETRIC PASS GATES  
Conductive stripes laterally abutting the dielectric lines are formed over a thin semiconductor layer on a gate dielectric. Angled halo ion implantation is performed to implant p-type dopants on...
US20090221105 MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of...
US20090212369 Gate Effective-Workfunction Modification for CMOS  
CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same...
US20090212372 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the...
US20090215278 SEMICONDUCTOR DEVICE MANUFACTURING METHOD  
Prior to a step of providing a stress layer covering a first transistor, a second transistor and a gate structure, another silicon oxide film is formed over the second transistor to form a silicon...
US20090206416 DUAL METAL GATE STRUCTURES AND METHODS  
Two dummy gate structures containing disposable material portions and metal portions, source and drain regions, and metal semiconductor alloy regions are formed on a semiconductor substrate. A...
US20090194820 CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS  
A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on...
US20090194821 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a...
US20090194816 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first...
US20090194789 METHOD OF CREATING A STRAINED CHANNEL REGION IN A TRANSISTOR BY DEEP IMPLANTATION OF STRAIN-INDUCING SPECIES BELOW THE CHANNEL REGION  
By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided,...
US20090186456 Method of Manufacturing Semiconductor Device using Salicide Process  
A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region;...
US20090186455 DISPOSABLE METALLIC OR SEMICONDUCTOR GATE SPACER  
A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as...
US20090179308 Method of Manufacturing a Semiconductor Device  
According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a semiconductor structure; forming a stress liner...
US20090181504 METHOD FOR MANUFACTURING A CMOS DEVICE HAVING DUAL METAL GATE  
A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a...
US20090173967 STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER  
This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded...
US20090166629 REDUCING GATE CD BIAS IN CMOS PROCESSING  
A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over...
US20090170254 Method of Manufacturing a Semiconductor Device  
In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are...
US20090152639 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement  
Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the...
US20090152637 PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT  
A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In...
US20090152624 INTEGRATED CIRCUIT DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT DEVICE  
An integrated circuit device with a semiconductor body and a method for the production of a semiconductor device a provided. The semiconductor body comprises a cell field with a drift zone of a...
US20090142891 MASKLESS STRESS MEMORIZATION TECHNIQUE FOR CMOS DEVICES  
In one embodiment, the present invention provides a method of manufacturing a semiconducting device that includes providing a silicon containing substrate having PFET device and NFET device,...
US20090134469 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH DUAL FULLY SILICIDED GATE  
A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method comprises providing a first metal layer over a first electrode in a first region, and at...
US20090114993 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME  
A semiconductor device includes a silicon substrate; a P channel type field effect transistor including a first gate insulating film on the substrate, a first gate electrode on the first gate...
US20090114994 STRUCTURE OF MTCMOS CELL AND METHOD FOR FABRICATING THE MTCMOS CELL  
An architecture of the layout of the MTCMOS standard cell designed for low power consumption is supplemented so that the pick-up cells are included in the power line of the MTCMOS cell. Therefore,...
US20090108370 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
There have been provided a semiconductor device capable of preventing defects associated with etching, such as an increase in leak current, deterioration in film-coating properties and...
US20090101972 PROCESS FOR FABRICATING A FIELD-EFFECT TRANSISTOR WITH DOPING SEGREGATION USED IN SOURCE AND/OR DRAIN  
Source and/or drain regions of a transistor are first doped with an appropriate dopant and a metal is subsequently deposited. After heating, a silicide will displace the dopant, creating an...
US20090101983 Method of Achieving Dense-Pitch Interconnect Patterning in Integrated Circuits  
Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum...
US20090095981 Complementary metal oxide semiconductor device and method of manufacturing the same  
Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. The CMOS device comprises an epi-layer that may be formed on a substrate; a first...
US20090098692 Method for Fabricating a Semiconductor Gate Structure  
A method of making a semiconductor device is disclosed. A mask if formed over a first and a second region of a semiconductor body, and a vertical diffusion barrier is formed in a region between the...
US20090090950 SEMICONDUCTOR DEVICES  
Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS...
Matches 1 - 50 out of 163 1 2 3 4 >