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US20150318307 SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE  
A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at...
US20150318218 SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE  
A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at...
US20150311207 Structure and Method for FinFET Device  
The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a plurality of first fin structures over a substrate. The first fin...
US20150311125 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A method of manufacturing a semiconductor CMOS device is provided. The method includes providing a semiconductor substrate, forming a first fin in a PMOS region and a second fin in an NMOS region...
US20150311124 SELECTIVELY DEGRADING CURRENT RESISTANCE OF FIELD EFFECT TRANSISTOR DEVICES  
A method includes selectively degrading a current capacity of a first finned-field-effect-transistor (finFET) relative to a second finFET by forming a material on a fin of the first finFET to...
US20150303304 METHOD FOR FORMING FIN FET STRUCTURE WITH DUAL-STRESS SPACERS  
This application discloses a Fin FET structure and a method for forming the same. In the Fin FET structure, there are lower stress spacers disposed over the lower portion of the fin's opposite...
US20150294915 INTEGRATED CIRCUITS HAVING FINFETS WITH IMPROVED DOPED CHANNEL REGIONS AND METHODS FOR FABRICATING SAME  
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a...
US20150279850 TRANSISTOR DEVICE WITH GATE BOTTOM ISOLATION AND METHOD OF MAKING THEREOF  
An embodiment relates to a transistor device including a pillar of semiconductor material extending vertically from a bottom portion in contact with an electrically conductive contact line, where...
US20150262885 INTEGRATED CIRCUITS WITH STRESSED SEMICONDUCTOR-ON-INSULATOR (SOI) BODY CONTACTS AND METHODS FOR FABRICATING THE SAME  
Integrated circuits with selectively stressed semiconductor-on-insulator (SOI) body contacts and methods for fabricating integrated circuits with selectively stressed SOI body contacts are...
US20150228755 INTEGRATED CIRCUITS WITH RELAXED SILICON / GERMANIUM FINS  
Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium...
US20150221770 EPITAXIALLY FORMING A SET OF FINS IN A SEMICONDUCTOR DEVICE  
Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of...
US20150221559 SEMICONDUCTOR DEVICE WITH TRANSISTOR AND METHOD OF FABRICATING THE SAME  
A method of fabricating a semiconductor device that includes forming a gate stack layer including a metal-containing layer on a semiconductor substrate having an NMOS region and a PMOS region,...
US20150214119 FORMATION OF FINS HAVING DIFFERENT HEIGHTS IN FIN FIELD EFFECT TRANSISTORS  
A method includes forming at least two fins of a fin field effect transistor (finFET) on a substrate and forming an insulator layer on the at least two fins. A portion of the insulator layer at a...
US20150206965 HIGH PERFORMANCE FINFET  
A FinFET is described having first, second, and third pluralities of fins with gate structures and source and drain regions formed on the fins so that PMOS transistors are formed on the first...
US20150206888 STATIC RANDOM ACCESS MEMORY AND FABRICATION METHODS THEREOF  
A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate. The method also includes forming a plurality of transistors on the...
US20150171085 FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FORMING THE SAME  
Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the...
US20150155281 Semiconductor Device and Method of Forming the Same  
A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure...
US20150145048 STRUCTURE AND METHOD FOR FORMING CMOS WITH NFET AND PFET HAVING DIFFERENT CHANNEL MATERIALS  
Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a...
US20150144962 COMPLEMENTARILY STRAINED FINFET STRUCTURE  
A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a...
US20150138862 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF  
A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower...
US20150137239 Semiconductor Device and Method of Manufacturing the Same  
To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second...
US20150137181 STRESS INDUCING CONTACT METAL IN FINFET CMOS  
A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a...
US20150132901 Semiconductor Device and Fabricating the Same  
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first...
US20150102419 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode...
US20150102414 PREVENTING EPI DAMAGE FOR CAP NITRIDE STRIP SCHEME IN A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE  
Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide...
US20150099334 METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER  
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer...
US20150079740 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING AN EMBEDDED SOURCE/DRAIN  
A method for fabricating a semiconductor device is provided. A first gate pattern and a second gate pattern are adjacent to each other and are formed on an active region of a substrate. The active...
US20150069506 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
An aspect of the present embodiment, there is provided a semiconductor device includes a high-voltage element, the high-voltage element including a substrate, a first semiconductor region with a...
US20150044829 Methods of Fabricating Semiconductor Devices Having Punch-Through Stopping Regions  
Methods of fabricating semiconductor devices are provided including providing a substrate having a first region and a second region, the substrate defining trenches in the first and second...
US20150041911 3D TRANSISTOR CHANNEL MOBILITY ENHANCEMENT  
A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of...
US20150041908 METHOD OF MANUFACTURING A FinFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FinFET DEVICE FORMED BY SAME  
A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins,...
US20150041906 METHODS OF FORMING STRESSED FIN CHANNEL STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES  
One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive...
US20150037945 EPITAXIALLY FORMING A SET OF FINS IN A SEMICONDUCTOR DEVICE  
Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of...
US20150035071 Semiconductor Device and Fabricating the Same  
The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second...
US20150008536 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE  
The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active...
US20140367787 METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES  
A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon...
US20140361377 RETROGRADE DOPED LAYER FOR DEVICE ISOLATION  
Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a...
US20140361335 DEVICE INCLUDING A TRANSISTOR HAVING A STRESSED CHANNEL REGION AND METHOD FOR THE FORMATION THEREOF  
A device includes a substrate, a P-channel transistor and an N-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second...
US20140332896 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME  
A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a...
US20140312426 6T SRAM ARCHITECTURE FOR GATE-ALL-AROUND NANOWIRE DEVICES  
A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of...
US20140235022 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate...
US20140206156 FINFET DEVICE AND METHOD OF MANUFACTURING SAME  
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate....
US20140197377 CMOS NANOWIRE STRUCTURE  
Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a...
US20140179072 SEMICONDUCTOR DEVICE HAVING EPITAXIAL SEMICONDUCTOR LAYER ABOVE IMPURITY LAYER  
The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial...
US20140167158 INTEGRATED DEVICE AND METHOD FOR FABRICATING THE INTEGRATED DEVICE  
The invention relates to the field of fabricating a semiconductor integrated circuit and particularly to an integrated device and a method for fabricating the integrated device in order to address...
US20140159038 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT STRUCTURE, PREPARATION METHOD THEREOF AND DISPLAY DEVICE  
Provided are a CMOS circuit structure, a preparation method thereof and a display device, wherein a PMOS region in the CMOS circuit structure is of a LTPS TFT structure, that is, the PMOS...
US20140145242 Fin-Last FinFET and Methods of Forming Same  
Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a...
US20140113418 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE  
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and...
US20140099758 SRAM Devices Utilizing Strained-Channel Transistors and Methods of Manufacture  
A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS...
US20140091398 SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE  
Provided is a semiconductor device including a first source and a first drain of a P-channel-type MISFET formed on a Ge wafer, which are made of a compound having a Ge atom and a nickel atom, a...