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US20080067604 Field effect transistor arrangement, memory device and methods of forming the same  
Sacrificial structures are provided on a substrate. A template fills a space between the sacrificial structures. The sacrificial structures are removed, where openings are formed in the template....
US20070202644 SCHOTTKY-BARRIER MOS TRANSISTOR ON A FULLY-DEPLETED SEMICONDUCTOR FILM AND PROCESS FOR FABRICATING SUCH A TRANSISTOR  
This process for manufacturing a Schottky-barrier MOS transistor on a fully depleted semiconductor film may include depositing a first layer of a first sacrificial material on an active zone of...
US20070148847 Method of Fabricating CMOS Image Sensor  
A method of fabricating a CMOS image sensor is provided. According to an embodiment, a device isolation layer is formed in a semiconductor substrate to define a device isolation region and an...
US20060088964 Method of forming SRAM cell  
A method of forming an SRAM cell, having two transfer transistors, two driver transistors, and two load devices which are connected with one another in the form of a flip-flop is provided. In...
US20060079046 METHOD AND STRUCTURE FOR IMPROVING CMOS DEVICE RELIABILITY USING COMBINATIONS OF INSULATING MATERIALS  
A method for improving hot carrier effects in complementary metal oxide semiconductor (CMOS) devices includes forming a first configuration of insulating material over a first group of the CMOS...
US20170170181 SPACER FOR DUAL EPI CMOS DEVICES  
Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor...
US20170170076 FINFET CMOS WITH Si NFET AND SiGe PFET  
A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si...
US20170162577 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF  
A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of...
US20170154820 FETS AND METHODS OF FORMING FETS  
An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial...
US20170140997 FINFET AND METHOD OF FORMING FIN OF THE FINFET  
A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching...
US20170092755 METHOD AND APPARATUS FOR POWER DEVICE WITH MULTIPLE DOPED REGIONS  
A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the...
US20170092546 FORMING A CMOS WITH DUAL STRAINED CHANNELS  
The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same...
US20170040436 METHODS FOR FABRICATING SEMICONDUCTOR DEVICE  
A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a...
US20170033019 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of...
US20170005010 Germanium-Based CMOS Comprising Silicon Cap Formed Over PMOS Region Having A Thickness Less Than That Over NMOS Region  
A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is...
US20160379979 INCLUDING LOW AND HIGH-VOLTAGE CMOS DEVICES IN CMOS PROCESS  
A device includes a substrate, a deep well, a first well, and a second well. The deep well is formed in the substrate. The first well includes a first portion formed on the deep well and a second...
US20160336321 DUAL FIN INTEGRATION FOR ELECTRON AND HOLE MOBILITY ENHANCEMENT  
A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial...
US20160336236 DUAL FIN INTEGRATION FOR ELECTRON AND HOLE MOBILITY ENHANCEMENT  
A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial...
US20160315018 METHODS OF FABRICATING FINFET SEMICONDUCTOR DEVICES INCLUDING DUMMY STRUCTURES  
Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate...
US20160307807 PUNCH-THROUGH-STOP AFTER PARTIAL FIN ETCH  
A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a...
US20160293611 SELECTIVELY DEGRADING CURRENT RESISTANCE OF FIELD EFFECT TRANSISTOR DEVICES  
A method includes selectively degrading a current capacity of a first finned-field-effect-transistor (finFET) relative to a second finFET by forming a material on a fin of the first finFET to...
US20160284600 Memory Cell Layout  
A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the...
US20160276225 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES  
Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through...
US20160204113 SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE  
A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source...
US20160190252 FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE METHOD AND DEVICE  
A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first...
US20160181244 SHORT CHANNEL EFFECT SUPPRESSION  
A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing...
US20160148847 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE  
A method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a first and a second voltage device portion, each including a first and a second conductive...
US20160133747 SEMICONDUCTOR TRANSISTOR HAVING A STRESSED CHANNEL  
A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The...
US20160118306 SEMICONDUCTOR DEVICE WITH BURIED METAL LAYER  
A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a...
US20160104800 Body-Tied, Strained-Channel Multi-Gate Device and Methods of Manufacturing Same  
A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor...
US20160104771 COMMON CONTACT OF N++ AND P++ TRANSISTOR DRAIN REGIONS IN CMOS  
Implementations of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one implementation, an integrated circuit is...
US20160099182 Backside Contacts for Integrated Circuit Devices  
A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the...
US20160093735 EMBEDDED CARBON-DOPED GERMANIUM AS STRESSOR FOR GERMANIUM nFET DEVICES  
Carbon-doped germanium stressor regions are formed in an nFET device region of a germanium substrate and at a footprint of a functional gate structure. The carbon-doped germanium stressor regions...
US20160087040 METHODS FOR HIGH-K METAL GATE CMOS WITH SiC AND SiGe SOURCE/DRAIN REGIONS  
A method of manufacturing a semiconductor device includes forming a PMOS region and an NMOS region in a semiconductor substrate, forming dummy gate structures in the PMOS and NMOS regions, and...
US20160086952 PREVENTING EPI DAMAGE FOR CAP NITRIDE STRIP SCHEME IN A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE  
Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide...
US20160086946 CMOS DEVICE AND METHOD FOR MANUFACTURING THE SAME  
An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on...
US20160086859 Dummy Gate for a High Voltage Transistor Device  
The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped...
US20160064289 SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF  
A method for forming a semiconductor structure includes sequentially providing a semiconductor substrate having NFET regions and NFET regions; forming an insulation layer on the semiconductor...
US20160047059 TWO-DIMENSIONAL LARGE-AREA GROWTH METHOD FOR CHALCOGEN COMPOUND, METHOD FOR MANUFACTURING CMOS-TYPE STRUCTURE, FILM OF CHALCOGEN COMPOUND, ELECTRONIC DEVICE COMPRISING FILM OF CHALCOGEN COMPOUND, AND CMOS-TYPE STRUCTURE  
Provided is a two-dimensional large-area growth method for a chalcogen compound, the method including: depositing a film of a transition metal element or a Group V element on a substrate;...
US20160043004 METHOD FOR MANUFACTURING CMOS STRUCTURE  
The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the...
US20160035854 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE  
A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the...
US20160035728 RETROGRADE DOPED LAYER FOR DEVICE ISOLATION  
Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a...
US20160027703 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially...
US20150380319 FIN-SHAPED FIELD-EFFECT TRANSISTOR PROCESS  
A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are...
US20150380311 TUNNELING FIELD EFFECT TRANSISTOR DEVICE AND RELATED MANUFACTURING METHOD  
A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a...
US20150371904 PATTERNING PROCESS FOR FIN IMPLANTATION  
After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces...
US20150349065 TRANSISTOR STRUCTURE INCLUDING EPITAXIAL CHANNEL LAYERS AND RAISED SOURCE/DRAIN REGIONS  
The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel...
US20150340292 PATTERNING PROCESS FOR FIN IMPLANTATION  
After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces...
US20150325686 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FIN RELAXATION, AND RELATED STRUCTURES  
Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form...
US20150325681 METHODS OF FABRICATING INTEGRATED CIRCUITS  
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first...