Match Document Document Title
US20130178024 In Situ Doping and Diffusionless Annealing of Embedded Stressor Regions in PMOS and NMOS Devices  
Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and...
US20130029463 Methods of Forming a PMOS Device with In Situ Doped Epitaxial Source/Drain Regions  
Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting...
US20120007052 Apparatus, System, and Method for Dual-Channel Nanowire FET Device  
An apparatus, system, and method for dual-channel FET devices is presented. In some embodiments, the nanowire FET device may include a first transistor on a substrate, where the first transistor...
US20090194816 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first...
US20080254580 Realization of Self-Positioned Contacts by Epitaxy  
Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region...
US20080173941 ETCHING METHOD AND STRUCTURE IN A SILICON RECESS FOR SUBSEQUENT EPITAXIAL GROWTH FOR STRAINED SILICON MOS TRANSISTORS  
A semiconductor integrated circuit device comprising a semiconductor substrate, e.g., silicon wafer, silicon on insulator. The device has a dielectric layer overlying the semiconductor substrate...
US20070148848 METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE  
Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second...
US20070059875 Semiconductor device and method of manufacturing the same, and semiconductor substrate and method of manufacturing the same  
A method of manufacturing a semiconductor device including a substrate; an insulating film formed thereon; a first semiconductor layer where strain is induced in the directions parallel to the...
US20070052035 Method and apparatus for reducing optical crosstalk in CMOS image sensors  
An image sensor in which the metal interconnects are coated with an anti-reflective coating is disclosed. The top, bottom and sides of the metal interconnects may be coated to reduce reflection...
US20060275972 Method of fabricating CMOS inverters and integrated circuits utilizing strained surface channel MOSFETs  
A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed...
US20060118878 CMOS device with selectively formed and backfilled semiconductor substrate areas to improve device performance  
An NMOS and PMOS device pair having a selected stress level and type exerted on a respective channel region and method for forming the same, the method including providing a semiconductor...
US20050153498 Method of manufacturing p-channel MOS transistor and CMOS transistor  
A method of manufacturing a p-channel MOS transistor including forming a structure by subsequently stacking gate insulating layer pattern and a gate conductive layer pattern on a semiconductor...
US20050124129 Method of fabrication of silicon-gate MIS transistor  
Disclosed is a method for manufacturing a semiconductor device, the method includes forming an insulator layer on a crystalline silicon substrate; forming selectively a silicon layer on the...
US20150214112 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME  
Various embodiments provide semiconductor devices and methods for forming the same. A substrate having a dielectric layer formed thereon is provided. The dielectric layer has six openings. A gate...
US20150115321 SUBSTRATE STRUCTURE, COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE  
A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate...
US20150064861 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An...
US20150035062 INTEGRATED CIRCUITS HAVING FINFETS WITH IMPROVED DOPED CHANNEL REGIONS AND METHODS FOR FABRICATING SAME  
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin...
US20150021692 METHOD OF LOCALIZED MODIFICATION OF THE STRESSES IN A SUBSTRATE OF THE SOI TYPE, IN PARTICULAR FD SOI TYPE, AND CORRESPONDING DEVICE  
A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting...
US20140322873 HIGH PERFORMANCE STRESS-ENHANCED MOSFETS USING SI:C AND SIGE EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE  
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a stressing layer on a substrate. The method may include doping the stressing...
US20140227838 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns...
US20140110793 CMOS TRANSISTOR AND FABRICATION METHOD  
Exemplary embodiments provide transistors and methods for forming the transistors. An exemplary CMOS transistor can be formed by epitaxially forming a first stress layer in/on a semiconductor...
US20130299876 Method For Improving Selectivity Of EPI Process  
The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material...
US20130256806 SEMICONDUCTOR DEVICE INCLUDING CONTACT HOLES AND METHOD FOR FORMING THE SAME  
A semiconductor device including contact holes and method for forming the same are provided. A dual-stress liner is formed on a substrate. A first, second and third dielectric layers are then...
US20130217195 Transistor Device and Method of Manufacture Thereof  
A method of forming transistors and structures thereof A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n type dopant. The NMOS...
US20120231590 Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device  
A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a...
US20120196412 HIGH PERFORMANCE STRESS-ENHANCED MOSFETS USING SI:C AND SIGE EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE  
A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and...
US20120193726 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device including an n-channel-type MISFET (Qn) having an Hf-containing insulating film (5), which is a high dielectric constant gate insulating film containing hafnium, a...
US20110309450 SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION THEREOF WITH MIXED METAL TYPES  
A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a...
US20100264495 High-K Metal Gate CMOS  
A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in...
US20100261323 METHOD OF FORMING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR  
A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has agate structure, a source...
US20100252800 NANOWIRE DEVICES FOR ENHANCING MOBILITY THROUGH STRESS ENGINEERING  
A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first...
US20100248434 Method for Fabricating Semiconductor Device  
A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first...
US20100244106 Fabrication and structure of asymmetric field-effect transistors using L-shaped spacers  
Fabrication of an asymmetric field-effect transistor (100) entails defining a gate electrode (262) above, and vertically separated by a gate dielectric layer (260) from, a channel-zone portion...
US20100216287 METHOD FOR REMOVING HARD MASKS ON GATES IN SEMICONDUCTOR MANUFACTURING PROCESS  
A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a...
US20100203690 MOSFET HAVING A CHANNEL REGION WITH ENHANCED STRESS AND METHOD OF FORMING SAME  
A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the substrate. A first layer is formed to...
US20100197089 METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH METAL-SEMICONDUCTOR COMPOUND SOURCE/DRAIN CONTACT REGIONS  
Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed...
US20100187635 SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN  
By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor...
US20100176454 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE  
A method is provided of manufacturing a semiconductor device comprising a first, n-type field effect transistor (1) and a second, p-type field effect transistor (2). The method comprises...
US20100148275 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A semiconductor device includes a first MIS transistor formed on a first active region, and a second MIS transistor formed on a second active region. The first MIS transistor includes a first gate...
US20100117158 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME  
To provide a technique capable of improving the reliability of a semiconductor device even if the downsizing thereof is advanced. The technical idea of the present invention lies in the...
US20100102394 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
It is to enhance a current increasing effect by increasing a stress applied on a channel of a transistor. The invention is characterized by comprising: side wall insulating films 33 and 53 formed...
US20090321839 Semiconductor device and method for manufacturing the same  
A semiconductor device includes a silicon substrate; an N-channel field-effect transistor including a first gate insulating film on the silicon substrate, a first gate electrode on the first gate...
US20090194821 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a...
US20090186456 Method of Manufacturing Semiconductor Device using Salicide Process  
A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region;...
US20090181504 METHOD FOR MANUFACTURING A CMOS DEVICE HAVING DUAL METAL GATE  
A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a...
US20090170254 Method of Manufacturing a Semiconductor Device  
In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are...
US20090108370 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
There have been provided a semiconductor device capable of preventing defects associated with etching, such as an increase in leak current, deterioration in film-coating properties and...
US20080303099 Semiconductor Device and Fabrication Method Thereof  
CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and...
US20080254579 Semiconductor device and fabrication thereof  
A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is...
US20080191286 Methods for manufacturing a CMOS device with dual dielectric layers  
The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first...