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US20120322215 COMMUNICATION  
An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the...
US20100134182 Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors  
An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are...
US20080237751 CMOS Structure and method of manufacturing same  
A CMOS structure includes a substrate (110, 310), an electrically insulating layer (120, 320) over the substrate, NMOS (130, 330) and PMOS (140, 340) semiconducting structures over the...
US20070252216 Semiconductor device and a method of manufacturing such a semiconductor device  
A semiconductor device, specifically a Complementary Metal Oxide Semiconductor (CMOS) device, has a substrate on which are formed first and second field effect transistors. Each of the field...
US20130069164 Intrinsic channel FET  
A novel semiconductor transistor is presented. The semiconductor structure has a MOSFET like structure, with the difference that the device channel is formed in an intrinsic region, so as to...
US20100267212 FABRICATION METHODS FOR RADIATION HARDENED ISOLATION STRUCTURES  
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation....
US20090194820 CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS  
A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on...
US20080073676 Method for fabricating semiconductor device and semiconductor device  
An n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate 100. The p-channel MOS transistor includes a gate electrode 102a, a first offset sidewall 103a...
US20070134866 Method for integrating carbon nanotube with CMOS chip into array-type microsensor  
The invention disclosed a method for integrating CMOS circuit chips with carbon nanotubes (CNTs) into array-type sensors with signal processors enclosed. The method provides low-temperature and...
US20090032882 SEMICONDUCTOR DEVICE HAVING INSULATED GATE FIELD EFFECT TRANSISTORS AND METHOD OF MANUFACTURING THE SAME  
N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the...
US20080203488 CMOS semiconductor device and method of fabricating the same  
Example embodiments provide a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the CMOS semiconductor device. The CMOS semiconductor device may...
US20080185659 Semiconductor device and a method of fabricating the device  
A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile...
US20120168866 STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS  
A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and...
US20120070948 ADJUSTING METHOD OF CHANNEL STRESS  
An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a...
US20100099269 SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME  
Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific...
US20090321842 Method for manufacturing semiconductor device including metal gate electrode and semiconductor device  
A first metal film mainly including Ta is formed on a gate insulating film in a region excluding an n MOS transistor formation region and then a polysilicon film is formed to cover the gate...
US20090212369 Gate Effective-Workfunction Modification for CMOS  
CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same...
US20080079084 Enhanced mobility MOSFET devices  
Semiconductor devices having enhanced mobility regions and methods of forming such devices are disclosed. In some embodiments, a method includes providing a SiGe layer on a supporting substrate,...
US20060094181 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING A TRENCH STRUCTURE  
Disclosed is a method for fabricating a semiconductor device capable of preventing a residue from being generated during etching a gate conductive layer and forming a plurality of trenches having...
US20150084133 TUNNELING FIELD EFFECT TRANSISTOR DEVICE AND RELATED MANUFACTURING METHOD  
A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a...
US20130230952 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING SAME  
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate...
US20100155848 Trigate static random-access memory with independent source and drain engineering, and devices made therefrom  
A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device...
US20090289379 Methods of Manufacturing Semiconductor Devices and Structures Thereof  
Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region...
US20090095981 Complementary metal oxide semiconductor device and method of manufacturing the same  
Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. The CMOS device comprises an epi-layer that may be formed on a substrate; a first...
US20090026550 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes: a silicon substrate; and a field effect transistor including a gate insulating film over the silicon substrate, a gate electrode on the gate insulating film, and...
US20150179648 MULTI-LAYER SEMICONDUCTOR STRUCTURES FOR FABRICATING INVERTER CHAINS  
Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and...
US20110070701 INTEGRATION SCHEME FOR STRAINED SOURCE/DRAIN CMOS USING OXIDE HARD MASK  
A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further...
US20100059827 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films,...
US20090212372 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the...
US20090134469 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH DUAL FULLY SILICIDED GATE  
A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method comprises providing a first metal layer over a first electrode in a first region, and at...
US20090032881 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME IN WHICH A MOBILITY CHANGE OF THE MAJOR CARRIER IS INDUCED THROUGH STRESS APPLIED TO THE CHANNEL  
A semiconductor device includes a semiconductor substrate, a gate structure formed on the semiconductor substrate, wherein the gate structure includes a gate electrode formed on the semiconductor...
US20080111155 ELECTRONIC DEVICE INCLUDING A TRANSISTOR HAVING A METAL GATE ELECTRODE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE  
An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region...
US20070284671 SEMICONDUCTOR DEVICE INCLUDING CMIS TRANSISTOR  
Gate electrodes made of polysilicon film are isolated and face each other by way of a side wall spacer portion that fills a gap formed above an isolation insulating film at the boundary of NMIS...
US20070257322 Hybrid Transistor Structure and a Method for Making the Same  
A topography (40) is provided which includes a device having a transistor formed from a stack of semiconductor layers (42/46). The different semiconductor layers are spaced apart by a gate (60)...
US20140183651 SEMICONDUCTOR DEVICE WITH METAL GATE AND HIGH-K MATERIALS AND METHOD FOR FABRICATING THE SAME  
A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first...
US20130168695 CMOS HAVING A SIC/SIGE ALLOY STACK  
A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate,...
US20120306021 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION  
A semiconductor device is provided that includes a first pair of P channel field effect transistors (PFET) with a common source connected to a voltage contact and a gate connected to a drain of...
US20110227094 STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS  
A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel...
US20100084713 Semiconductor device manufacturing method and semiconductor device  
A second mask is provided so as to cover a second gate pattern and a first gate pattern is heated to a temperature at which a material gas containing a first metal thermally decomposes,...
US20090309164 STRUCTURE AND METHOD TO INTEGRATE DUAL SILICIDE WITH DUAL STRESS LINER TO IMPROVE CMOS PERFORMANCE  
The present invention provides a semiconducting device including a substrate including a semiconducting surface having an n-type device in a first device region and a p-type device in a second...
US20090302390 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH DIFFERENT METALLIC GATES  
A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor cap (26) is formed over gate dielectric (24) and patterned to be present in a...
US20090227078 CMOS Devices having Dual High-Mobility Channels  
A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor...
US20090194789 METHOD OF CREATING A STRAINED CHANNEL REGION IN A TRANSISTOR BY DEEP IMPLANTATION OF STRAIN-INDUCING SPECIES BELOW THE CHANNEL REGION  
By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided,...
US20080299715 Method of Fabricating Self Aligned Schotky Junctions For Semiconductors Devices  
A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the...
US20080085577 METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR  
A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After...
US20070059874 Dual Metal Gate and Method of Manufacture  
Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal...
US20060001043 CMOS image sensor and fabricating method thereof  
A CMOS image sensor and fabricating method thereof are disclosed, by which a dark current can be reduced. The present invention includes a first conductive type semiconductor substrate divided...
US20150031178 METHOD OF CMOS MANUFACTURING UTILIZING MULTI-LAYER EPITAXIAL HARDMASK FILMS FOR IMPROVED GATE SPACER CONTROL  
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon...
US20140273365 METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES BY FORMING A REGION THAT INCLUDES A SCHOTTKY BARRIER LOWERING MATERIAL  
Various methods of forming conductive contacts to the source/drain regions of FinFET devices that involves forming a region comprised of a Schottkky barrier lowering material are disclosed. The...
US20130260518 PROCESS TO IMPROVE TRANSISTOR DRIVE CURRENT THROUGH THE USE OF STRAIN  
The present invention provides, in one embodiment, a P-type Metal Oxide Semiconductor (PMOS) device (100). The device (100) comprises a tensile-strained silicon layer (105) located on a...