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US20120220086 METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL)  
Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a...
US20120176193 DRIVER FOR A SEMICONDUCTOR CHIP  
A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type...
US20100176395 CMOS THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME AND ORGANIC LIGHT EMITTING DISPLAY DEVICE HAVING THE SAME  
A CMOS thin film transistor arrangement including a PMOS poly-silicon thin film transistor having a top gate configuration and a NMOS oxide thin film transistor having an inverted staggered bottom...
US20080251851 STRAIN ENHANCED SEMICONDUCTOR DEVICES AND METHODS FOR THEIR FABRICATION  
A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the...
US20090309166 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
The semiconductor device includes an n-channel transistor including n-type source/drain regions and a first gate electrode, a first sidewall insulating film formed on a side wall of the first gate...
US20060258074 Methods that mitigate excessive source/drain silicidation in full gate silicidation metal gate flows  
The present invention facilitates semiconductor fabrication by providing methods of fabrication that form metal silicide gates and mitigate formation of silicide region defects near channel...
US20130328112 SEMICONDUCTOR DEVICES HAVING IMPROVED GATE HEIGHT UNIFORMITY AND METHODS FOR FABRICATING SAME  
Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface...
US20080290428 USE OF ALLOYS TO PROVIDE LOW DEFECT GATE FULL SILICIDATION  
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate...
US20080280404 RESIDUE FREE PATTERNED LAYER FORMATION METHOD APPLICABLE TO CMOS STRUCTURES  
A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered...
US20080102572 Manufacturing method of semiconductor device  
The present invention provides a method of manufacturing a semiconductor device, which is simple in manufacturing process and easy to control formed positions of a tensile film and a compressive...
US20080073724 DOUBLE LAYER ETCH STOP LAYER STRUCTURE FOR ADVANCED SEMICONDUCTOR PROCESSING TECHNOLOGY  
A semiconductor device and a method for forming the same provides a double layer contact etch stop layer selectively formed over PMOS transistors with only a single silicon nitride contact etch...
US20060046371 Methods of forming gate electrodes in semiconductor devices  
Method for forming gate electrode in semiconductor device are disclosed. In one example, the method may include forming a gate oxide layer on a substrate having a region where a PMOS region and a...
US20050214998 Local stress control for CMOS performance enhancement  
A semiconductor device and method for forming the same for improving charge mobility in NMOS and PMOS devices simultaneously, the method including forming a first dielectric layer including a...
US20090020820 CHANNEL-STRESSED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION  
In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a...
US20080246092 Semiconductor device structure with strain layer and method of fabricating the semiconductor device structure  
A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and...
US20050161745 CMOS device, method for fabricating the same and method for generating mask data  
An NMIS gate implantation layer is generated by a method in which mask data of a P-type well implantation layer are added to mask data obtained by subtracting mask data of an NMIS-SD implantation...
US20080145985 EMBEDDED SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME  
The invention discloses a method for fabricating an embedded semiconductor memory device, comprising: preparing a semiconductor substrate comprising a region IA and a region IB; forming gate...
US20070158753 SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVICES OF SAME CONDUCTIVE TYPE ON SAME SUBSTRATE  
A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective...
US20090283835 METHOD FOR FABRICATING A DUAL WORKFUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF  
A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region...
US20090039441 MOSFET WITH METAL GATE ELECTRODE  
Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a...
US20070275522 METHOD TO ENHANCE CMOS TRANSISTOR PERFORMANCE BY INDUCING STRAIN IN THE GATE AND CHANNEL  
A method of manufacturing complementary metal oxide semiconductor transistors forms different types of transistors such as N-type metal oxide semiconductor (NMOS) transistors and P-type metal...
US20110012181 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVCIE HAVING CAPACITOR ELEMENT  
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell,...
US20090166629 REDUCING GATE CD BIAS IN CMOS PROCESSING  
A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over...
US20060086987 Method for manufacturing a semiconductor device with reduced floating body effect  
A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate,...
US20090263944 Method for making low Vt gate-first light-reflective-layer covered dual metal-gates on high-k CMOSFETs  
This invention proposes a method for making low Vt light-reflective-layer/dual-metal-gates/high-κ CMOSFETs with simple light-irradiation anneal and light-reflective-layer covered dual metal-gates...
US20080093673 Semiconductor device and fabrication method thereof  
A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first...
US20100087038 METHOD FOR N/P PATTERNING IN A GATE LAST PROCESS  
A method is provided that includes providing a substrate, forming a first gate structure in a first region and a second gate structure in a second region, the first and second gate structures each...
US20090152637 PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT  
A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In...
US20060199325 Semiconductor integrated circuit device advantageous for microfabrication and manufacturing method for the same  
A semiconductor integrated circuit device includes cells, each of the cells including a gate electrode, which is provided on the well, and first diffusion layers of a second conductivity type...
US20100013025 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
In a second direction, in a plan view, an n-channel MOS transistor and an expanding film are adjacent. Therefore, the n-channel MOS transistor receives a positive stress in the direction in which...
US20090090950 SEMICONDUCTOR DEVICES  
Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS...
US20070048920 Methods for dual metal gate CMOS integration  
Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask...
US20130285155 III-V LAYERS FOR N-TYPE AND P-TYPE MOS SOURCE-DRAIN CONTACTS  
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to...
US20080157118 INTEGRATED CIRCUIT SYSTEM EMPLOYING STRAINED TECHNOLOGY  
An integrated circuit system that includes: providing a substrate with a PMOS device and an NMOS device; forming an NMOS shallow recess within the substrate; forming a PMOS recess within the...
US20100090288 METHOD OF FORMING SOURCE AND DRAIN OF A FIELD-EFFECT-TRANSISTOR AND STRUCTURE THEREOF  
A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but...
US20070032008 MOS semiconductor devices having polysilicon gate electrodes and high dielectric constant gate dielectric layers and methods of manufacturing such devices  
A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The...
US20060205134 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD FOR REGULATING SPEED OF FORMING AN INSULATING FILM  
A method for manufacturing a semiconductor device including sidewall insulating films with different thicknesses includes the steps of (a) selectively forming first and second gate electrode...
US20060148145 Method of manufacturing an RF MOS semiconductor device  
A method of manufacturing an RF MOS semiconductor device includes: forming a gate stack including a gate oxide layer and a gate polysilicon layer on a silicon substrate; forming source/drain...
US20100013023 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE  
A semiconductor device includes a first MISFET having a first conduction type channel and formed on a semiconductor substrate; a second MISFET having a second conduction type channel and formed on...
US20090014806 Semiconductor Device and Method for Manufacturing the Same  
A semiconductor device and method of manufacturing thereof. The semiconductor device has at least one NMOS device and at least one PMOS device provided on a substrate. An electron channel of the...
US20070287244 ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS  
A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a...
US20090206416 DUAL METAL GATE STRUCTURES AND METHODS  
Two dummy gate structures containing disposable material portions and metal portions, source and drain regions, and metal semiconductor alloy regions are formed on a semiconductor substrate. A...
US20080054363 DUAL GATE CMOS SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A dual gate Complementary Metal Oxide Semiconductor (CMOS) device includes a gate electrode of PMOS transistor implanted with germanium and indium ions and formed on a gate insulating film; a gate...
US20050048712 Method for forming high voltage complementary metal-oxide semiconductor by utilizing retrograde ion implantation  
A method for forming a high voltage complementary metal-oxide semiconductor (high voltage CMOS) by utilizing a retrograde ion implantation step. The present invention utilizes a retrograde ion...
US20150061029 CMOS TRANSISTORS AND FABRICATION METHOD THEREOF  
A method is provided for forming CMOS transistors. The method includes providing a semiconductor substrate having at least one first region and at least one second region; and forming a first gate...
US20140035062 TRANSISTOR DEVICE AND A METHOD OF MANUFACTURING SAME  
A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second...
US20140035059 SEMICONDUCTOR DEVICE HAVING METALLIC SOURCE AND DRAIN REGIONS  
Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of...
US20080142855 MOS TRANSISTOR, METHOD FOR MANUFACTURING THE MOS TRANSISTOR, CMOS SEMICONDUCTOR DEVICE INCLUDING THE MOS TRANSISTOR, AND SEMICONDUCTOR DEVICE INCLUDING THE CMOS SEMICONDUCTOR DEVICE  
A MOS transistor includes a silicon substrate, a gate insulating film disposed on the silicon substrate, a gate electrode disposed on the gate insulating film, source/drain regions disposed at...
US20070059873 Fabrication of single or multiple gate field plates  
A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a...
US20150187772 OPTIMIZED LAYOUT FOR RELAXED AND STRAINED LINER IN SINGLE STRESS LINER TECHNOLOGY  
An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors is adjusted for improved transistor...