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US20150031177 METHOD OF CMOS MANUFACTURING UTILIZING MULTI-LAYER EPITAXIAL HARDMASK FILMS FOR IMPROVED EPI PROFILE  
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated...
US20110086476 Methods of Forming Field Effect Transistors on Substrates  
The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field...
US20090020791 PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT ETCH-STOP LINER LAYERS  
Exemplary embodiments provide IC CMOS devices having dual stress layers and methods for their manufacture using a buffer layer stack between the two types of the stress layers. The buffer layer...
US20150228768 Tunneling Field Effect Transistor with New Structure and Preparation Method Thereof  
A tunneling field effect transistor with a new structure and a preparation method thereof are provided. The tunneling field effect transistor includes an active region between a source and a...
US20090098692 Method for Fabricating a Semiconductor Gate Structure  
A method of making a semiconductor device is disclosed. A mask if formed over a first and a second region of a semiconductor body, and a vertical diffusion barrier is formed in a region between...
US20130337621 NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES  
A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall...
US20120302019 NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES  
A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall...
US20080191285 CMOS devices with schottky source and drain regions  
A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension...
US20110089498 INTEGRATION OF LOW AND HIGH VOLTAGE CMOS DEVICES  
A method of fabricating a semiconductor device is provided that includes providing a semiconductor substrate having a first portion and a second portion, forming a first transistor in the first...
US20080203484 FIELD EFFECT TRANSISTOR ARRANGEMENT AND METHOD OF PRODUCING A FIELD EFFECT TRANSISTOR ARRANGEMENT  
A field effect transistor arrangement and a fabrication method thereof. The field effect transistor arrangement includes: a substrate having a first crystal surface orientation; a first layer...
US20070231988 Method of fabricating nanowire memory device and system of controlling nanowire formation used in the same  
A method of fabricating a nanowire memory device, and a system of controlling nanowire formation used in the same method are provided. In the method of fabricating a nanowire memory device which...
US20150053928 SILICON AND SILICON GERMANIUM NANOWIRE FORMATION  
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are...
US20110275184 Semiconductor Device  
A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode...
US20100041189 SELECTIVE REMOVAL OF A SILICON OXIDE LAYER  
A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the...
US20060148157 Geometrically optimized spacer to improve device performance  
A CMOS device with trapezoid shaped spacers and a method for forming the same with improved critical dimension control and improved salicide formation, the CMOS device including a semiconductor...
US20150171166 FORMATION OF NICKEL SILICON AND NICKEL GERMANIUM STRUCTURE AT STAGGERED TIMES  
Systems and methods are provided for generating a semiconductor device on a single semiconductor substrate. A single semiconductor substrate is generated that includes a Silicon material portion...
US20090017586 CHANNEL STRESS MODIFICATION BY CAPPED METAL-SEMICONDUCTOR LAYER VOLUME CHANGE  
A method for fabricating a field effect device, such as a field effect transistor, uses a first metal-semiconductor layer, such as a first metal-silicide layer, adjacent a channel in the field...
US20100072553 METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE  
A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile...
US20080090348 Gate-assisted silicon-on-insulator on bulk wafer and its application to floating body cell memory and transistors  
Embodiments of methods and apparatus for a gate-assisted silicon-on-insulator on bulk wafer and its application to floating body cells are generally described herein. Other embodiments may be...
US20080143423 SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR  
The present invention is directed to realize high manufacture yield and compensate variations in threshold voltage of a MOS transistor with small overhead. A semiconductor integrated circuit...
US20090142891 MASKLESS STRESS MEMORIZATION TECHNIQUE FOR CMOS DEVICES  
In one embodiment, the present invention provides a method of manufacturing a semiconducting device that includes providing a silicon containing substrate having PFET device and NFET device,...
US20070126063 Semiconductor device and semiconductor device manufacturing method  
A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation...
US20070249138 Buried dielectric slab structure for CMOS imager  
A substrate structure, and method of forming the structure, are provided. The structure, which may be used for a CMOS imager device, is provided with a buried dielectric structure. Recesses are...
US20050020000 Transistor manufacturing method, electro-optic device and electronic instrument  
In a transistor having a top gate structure, a portion of a gate insulating film is formed using a coating method. At this time, the size of the semiconductor film on which the coating film is...
US20070093014 Method for preventing doped boron in a dielectric layer from diffusing into a substrate  
The present invention provides a method for preventing doped boron in a dielectric layer from diffusing into a substrate. First, at least one gate is formed on a periphery circuit area and a...
US20050173766 Semiconductor memory and manufacturing method thereof  
In a semiconductor memory, and a manufacturing method thereof, the semiconductor memory includes a gate stack structure formed on a semiconductor substrate, first and second impurity regions...
US20120139054 Device Having Adjustable Channel Stress and Method Thereof  
The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device (200, 300), comprising a semiconductor substrate (202, 302); a...
US20110248351 MULTI-THRESHOLD VOLTAGE DEVICE AND METHOD OF MAKING SAME  
An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. An exemplary method includes providing a substrate; forming a first gate over the substrate...
US20080315191 Organic Thin Film Transistor Array and Method of Manufacturing the Same  
An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi...
US20080211032 Semiconduct Device and Method of Manufacturing Such a Semiconductor Device  
The invention relates to a CMOS device (10) with an NMOST I and PMOST 2 having gate regions (1D,2D) comprising a compound containing both a metal and a further element. According to the invention...
US20140231871 METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING  
An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second...
US20140091361 METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING  
An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second...
US20070264765 METHOD OF MANUFACTURING METAL OXIDE SEMICONDUCTOR AND COMPLEMENTARY METAL OXIDE SEMICONDUCTOR  
A method of manufacturing a metal oxide semiconductor is provided. The method includes forming an offset spacer and a disposable spacer around the offset spacer. Then, forming a plurality of...
US20140239407 REPLACEMENT METAL GATE TRANSISTOR WITH CONTROLLED THRESHOLD VOLTAGE  
A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the...
US20060281291 Method for manufacturing a metal-semiconductor contact in semiconductor components  
A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art...
US20110269277 Reduced STI Topography in High-K Metal Gate Transistors by Using a Mask After Channel Semiconductor Alloy Deposition  
In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate...
US20060263962 Methods of enabling polysilicon gate electrodes for high-k gate dielectrics  
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as...
US20090221105 MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of...
US20090221115 REDUCTION OF MEMORY INSTABILITY BY LOCAL ADAPTATION OF RE-CRYSTALLIZATION CONDITIONS IN A CACHE AREA OF A SEMICONDUCTOR DEVICE  
By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the...
US20060019438 Semiconductor device and method of manufacturing the same  
A semiconductor device is disclosed, which includes an n-channel MISFET including a first gate electrode and a first spacer formed on a side surface of the first gate electrode, the first spacer...
US20080164530 Integrated circuits with stress memory effect and fabrication methods thereof  
Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region....
US20070152277 MOS field-effect transistor and manufacturing method thereof  
To provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and...
US20090267160 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device comprises an anti-fuse element. The anti-fuse element includes a semiconductor substrate, a first gate insulating film, a first gate electrode, a high-concentration impurity...
US20100062575 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate;...
US20100032727 BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HOT) DIRECT SILICON BONDED (DSB) SUBSTRATES  
Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS...
US20080128750 Method and system for providing a metal oxide semiconductor device having a drift enhanced channel  
A method and system for providing a metal oxide semiconductor (MOS) device are described. The method and system include providing a source, a drain, and a channel residing between the source and...
US20130105907 MOS DEVICE AND METHOD OF MANUFACTURING THE SAME  
The present invention relates to a MOS device and method of manufacturing the same. The device comprises a semiconductor substrate; a channel formed in the semiconductor substrate; a gate stack...
US20060278934 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
A semiconductor device including, on a substrate, a first conduction type MOS transistor having a gate electrode provided in a first trench formed in an insulation film on the substrate, and a...
US20100207182 Implementing Variable Threshold Voltage Transistors  
A circuit and method for implementing variable threshold voltage transistors in a complementary metal oxide semiconductor (CMOS) semiconductor chip, and a design structure on which the subject...
US20130034940 Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET  
A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe...