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US20070200179 Strain enhanced CMOS architecture with amorphous carbon film and fabrication method of forming the same  
A strain enhanced CMOS device using amorphous carbon films and fabrication methods of forming the same. The amorphous carbon (a-C) film, such as fluorinated amorphous carbon (a-C:F), is formed of...
US20090087955 METHOD FOR REMOVING HARD MASKS ON GATES IN SEMICONDUCTOR MANUFACTURING PROCESS  
A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a...
US20070069302 Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby  
A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by...
US20070264766 NOS NON-VOLATILE MEMORY CELL AND METHOD OF OPERATING THE SAME  
A nitride/oxide/semiconductor (NOS) non-volatile memory cell formed in an n-well, having no control gate and capable of storing two bits is provided. The NOS non-volatile memory cell includes at...
US20080224218 CMOS STRUCTURE INCLUDING DIFFERENTIAL CHANNEL STRESSING LAYER COMPOSITIONS  
A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer...
US20070298596 Method of removing a photoresist pattern, method of forming a dual polysilicon layer using the removing method and method of manufacturing a semiconductor device using the removing  
In a method of removing a photoresist pattern, a photoresist pattern may be formed on an object layer. Impurities may be implanted into the object layer by a first ion implantation process...
US20110006370 EFFECTING SELECTIVITY OF SILICON OR SILICON-GERMANIUM DEPOSITION ON A SILICON OR SILICON-GERMANIUM SUBSTRATE BY DOPING  
The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behaviour according to a difference in...
US20130228873 Apparatus and Method for High Voltage MOS Transistor  
A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the...
US20080272414 Image sensing cell, device, method of operation, and method of manufacture  
An image sensing device can include one or more image sensing cells. Each image sensing cell can have a charge store element formed from a semiconductor material doped to a first conductivity...
US20050136583 Advanced strained-channel technique to improve CMOS performance  
A method of improving CMOS device performance, comprising the following steps. A structure having a gate electrode formed thereover and a channel formed thereunder is provided. The gate electrode...
US20150087121 CMOS STRUCTURES AND METHODS FOR IMPROVING YIELD  
A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress...
US20060208318 MOS field effect semiconductor device and method for fabricating the same  
A high-performance CMOS field effect semiconductor device using metal gate electrodes. An n-type gate electrode and a p-type gate electrode are formed by using a same metal and differ in nitrogen...
US20050186722 Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions  
Stress in a silicon nitride contact etch stop layer on a CMOS structure having NMOS and PMOS devices is selectively relieved by selective implantation of oxygen-containing or carbon-containing...
US20080124855 Modulation of Stress in ESL SiN Film through UV Curing to Enhance both PMOS and NMOS Transistor Performance  
An example embodiment of a method of forming a semiconductor device comprising the following. We form at least a first transistor over a first region of a substrate and forming at least a second...
US20090283829 FINFET WITH A V-SHAPED CHANNEL  
A fin-type field effect transistor (finFET) structure comprises a substrate having a planar upper surface, an elongated fin on the planar upper surface of the substrate (wherein the length and the...
US20130102117 Manufacturing Processes for Field Effect Transistors Having Strain-Induced Chanels  
One embodiment relates to a method of semiconductor manufacture. In this method, a strain inducing layer is formed over a p-type field effect transistor structure and an n-type field effect...
US20140015064 CMOS DEVICES AND FABRICATION METHOD  
A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes...
US20140315360 Method of Scavenging Impurities in Forming a Gate Stack Having an Interfacial Layer  
A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial...
US20080182370 METHODS FOR FABRICATING LOW CONTACT RESISTANCE CMOS CIRCUITS  
Methods for fabricating low contact resistance CMOS integrated circuits are provided. In accordance with an embodiment, a method for fabricating a CMOS integrated circuit including an NMOS...
US20070099372 Device having active regions of different depths  
An SOI device having SOI layers at two or more different depths below the surface of active regions of the device. Transistors for high-speed digital applications may be formed in the shallower...
US20090085122 POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT  
The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The...
US20080203381 Forming arsenide-based complementary logic on a single substrate  
In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium...
US20050035410 Semiconductor diode with reduced leakage  
A diode 100 is formed on a silicon-on-insulator substrate that includes a silicon layer overlying an insulator layer 142. An active region is formed in the silicon layer and includes a p-doped...
US20100109090 CMOS LATCH-UP IMMUNITY  
Latch-up of CMOS devices (20, 20′) is improved by using a structure (40, 40′, 80) having electrically coupled but floating doped regions (64, 64′; 65, 65′) between the N-channel (44) and P-channel...
US20090294801 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE  
Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate...
US20140001474 CMOS DEVICE AND FABRICATION METHOD  
Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and fabrication methods. An exemplary CMOS device can be formed by providing a first dummy gate over a...
US20050136580 Hydrogen free formation of gate electrodes  
The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be...
US20090179308 Method of Manufacturing a Semiconductor Device  
According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a semiconductor structure; forming a stress liner...
US20120223364 TRANSISTORS AND METHODS OF MANUFACTURING THE SAME  
In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first...
US20110241120 Field Effect Transistor Device and Fabrication  
A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first...
US20110062524 GATE STRUCTURES OF CMOS DEVICE AND METHOD FOR MANUFACTURING THE SAME  
Gate structures of CMOS device and the method for manufacturing the same are provided. A substrate having an NMOS region, a PMOS region, and a work function modulation layer disposed on the NMOS...
US20110006371 INDUCING STRESS IN CMOS DEVICE  
A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon...
US20100044799 METHOD FOR MANUFACTURING A P-TYPE MOS TRANSISTOR, METHOD FOR MANUFACTURING A CMOS-TYPE SEMICONDUCTOR APPARATUS HAVING THE P-TYPE MOS TRANSISTOR, AND CMOS-TYPE SEMICONDUCTOR APPARATUS MANUFACTURED USING THE MANUFACTURING METHOD  
A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate...
US20100025770 GATE DIELECTRICS OF DIFFERENT THICKNESS IN PMOS AND NMOS TRANSISTORS  
By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage...
US20060255901 Production of microelectromechanical systems (mems) using the high-temperature silicon fusion bonding of wafers  
The invention relates to a method for manufacturing MEMS devices, in which the sensor and the electronics for processing the sensor signal are monolithically integrated.
US20060084217 Plasma impurification of a metal gate in a semiconductor fabrication process  
A semiconductor fabrication includes forming a gate dielectric overlying a semiconductor substrate and depositing a metal gate film overlying the gate dielectric. Following deposition of the metal...
US20090075442 Metal Stress Memorization Technology  
A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method...
US20090039436 High Performance Metal Gate CMOS with High-K Gate Dielectric  
A CMOS structure is disclosed in which both type of FET devices have gate insulators containing high-k dielectrics, and gates containing metals. The threshold of the two type of devices are...
US20080081406 Method of Fabricating Semiconductor Device Having Dual Stress Liner  
A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate...
US20100164006 GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM  
A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS...
US20070105325 Method of manufacturing CMOS devices by the implantation of N- and P-type cluster ions  
A method of manufacturing a semiconductor device is described, wherein clusters of N- and P-type dopants are implanted to form the transistor structures in CMOS devices. For example,...
US20080283927 Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit  
System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment comprises manufacturing an integrated circuit, comprising forming a trench in an...
US20080023772 Semiconductor device including a germanium silicide film on a selective epitaxial layer  
A process for manufacturing a semiconductor device includes: forming first contact holes in a dielectric film for a PMOS transistor; depositing germanium on the source/drain regions of the PMOS...
US20070099360 INTEGRATED CIRCUITS HAVING STRAINED CHANNEL FIELD EFFECT TRANSISTORS AND METHODS OF MAKING  
An integrated circuit is provided that includes a substrate, a p-type field effect transistor, a compressive nitride layer, n-type field effect transistor, a tensile nitride layer, and a mask. The...
US20080290427 USE OF DOPANTS TO PROVIDE LOW DEFECT GATE FULL SILICIDATION  
The invention provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming an NMOS gate structure...
US20080293193 USE OF LOW TEMPERATURE ANNEAL TO PROVIDE LOW DEFECT GATE FULL SILICIDATION  
Provided is a method for manufacturing a semiconductor device that includes forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode....
US20060172480 Single metal gate CMOS device design  
A semiconductor device includes a PMOS transistor formed on a substrate structure. The PMOS transistor includes a source and a drain each including a diffusion region in the substrate structure, a...
US20080116521 CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same  
A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile...
US20060071285 Inducing strain in the channels of metal gate transistors  
In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than...
US20070184600 Stressed-channel CMOS transistors  
Methods for forming portions of source and drain (S/D) regions of a first ensuing transistor (40) to include a semiconductor material (47) having a different composition of non-dopant elements...