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US20080290419 LOW ON RESISTANCE CMOS TRANSISTOR FOR INTEGRATED CIRCUIT APPLICATIONS  
An array of power transistors on a semiconductor chip has serpentine gates separated by alternating source and drain regions. The gates combine rounded ends and rectangular sections joining the...
US20070249112 DIFFERENTIAL SPACER FORMATION FOR A FIELD EFFECT TRANSISTOR  
A method for manufacturing an integrated circuit includes providing one or more n-type field effect transistor and one or more p-type field effect transistor on a semiconductor substrate. Each of...
US20090218633 CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS  
A recessed transistor configuration may be provided selectively for one type of transistor, such as N-channel transistors, thereby enhancing strain-inducing efficiency and series resistance, while...
US20070105299 DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE  
A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a...
US20090224302 SEMICONDUCTOR DEVICE WITH INHERENT CAPACITANCES AND METHOD FOR ITS PRODUCTION  
A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In...
US20110031503 DEVICE WITH STRESSED CHANNEL  
An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials...
US20100210081 STRESS MEMORIZATION DIELECTRIC OPTIMIZED FOR NMOS AND PMOS  
A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors.
US20120074501 USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES  
Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field...
US20050269644 Forming integrated circuits with replacement metal gate electrodes  
In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized....
US20130214363 MANUFACTURING METHOD FOR A DEVICE WITH TRANSISTORS STRAINED BY SILICIDATION OF SOURCE AND DRAIN ZONES  
A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.
US20060046370 Method of manufacturing a transistor with void-free gate electrode  
A method of manufacturing a MOS transistor with a void-free gate electrode is provided. A gate oxide film may be formed on a semiconductor, and a poly silicon film for a gate electrode may be...
US20060024959 Thin tungsten silicide layer deposition and gate metal integration  
A method for depositing layers of a gate electrode is provided. The method includes depositing a doped polysilicon layer, a thin tungsten silicide layer, and a metal layer. In one aspect, the...
US20110049630 Stressed Source/Drain CMOS and Method of Forming Same  
A complementary metal-oxide semiconductor (CMOS) structure includes a substrate and a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate. Each...
US20120228717 SCHOTTKY DIODE AND METHOD OF MANUFACTURE  
A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells (16) for forming CMOS devices and second wells (18) for forming Schottky devices. Then,...
US20070096196 Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement  
A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a...
US20130234254 METHOD OF HYBRID HIGH-K/METAL-GATE STACK FABRICATION  
A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation...
US20150214116 LOW LEAKAGE PMOS TRANSISTOR  
A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high...
US20120064679 METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME  
A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the...
US20110074493 CONFIGURABLE NP CHANNEL LATERAL DRAIN EXTENDED MOS-BASED TRANSISTOR  
An integrated circuit containing a configurable dual n/p-channel 3-D resurf high voltage MOS field effect transistor (MOSFET) is disclosed. An n-channel drain is coterminous with a p-channel...
US20150001631 CMOS TECHNOLOGY INTEGRATION  
Complementary metal oxide semiconductor (CMOS) devices include input/output (I/O) devices and core function devices. A method includes forming first conduction type wells for the I/O devices and...
US20090218631 SRAM CELL HAVING ASYMMETRIC PASS GATES  
Conductive stripes laterally abutting the dielectric lines are formed over a thin semiconductor layer on a gate dielectric. Angled halo ion implantation is performed to implant p-type dopants on...
US20090114994 STRUCTURE OF MTCMOS CELL AND METHOD FOR FABRICATING THE MTCMOS CELL  
An architecture of the layout of the MTCMOS standard cell designed for low power consumption is supplemented so that the pick-up cells are included in the power line of the MTCMOS cell. Therefore,...
US20060033167 Reduced-step CMOS processes for low-cost radio frequency identification devices  
Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed...
US20110249489 Nanowire Circuits in Matched Devices  
An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first...
US20080318372 MANUFACTURING METHOD OF HIGH-LINEARITY AND HIGH-POWER CMOS STRUCTURE  
This invention relates to a method for making a high-linearity and high-power CMOS structure and particularly to a field plate technology that is applied to a CMOS component, in which the field...
US20060166423 Removal spacer formation with carbon film  
A method of making a CMOS device, and a product made by the process. The process includes applying a layer of a carbon film or carbon-containing compound to a substrate. A section of the carbon is...
US20140021556 SPACER SHAPER FORMATION WITH CONFORMAL DIELECTRIC FILM FOR VOID FREE PMD GAP FILL  
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral...
US20080182371 METHOD FOR FORMING SILICON/GERMANIUM CONTAINING DRAIN/SOURCE REGIONS IN TRANSISTORS WITH REDUCED SILICON/GERMANIUM LOSS  
By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even...
US20090173967 STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER  
This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded...
US20070164366 Mitigation of gate oxide thinning in dual gate CMOS process technology  
Excessive thinning of a thin oxide in a dual gate CMOS fabrication process is mitigated. A thick gate oxide utilized to form high voltage transistors is selectively patterned to leave some thick...
US20150171093 STRUCTURE AND METHOD FOR A SRAM CIRCUIT  
The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size;...
US20130235652 STRUCTURE AND METHOD FOR A SRAM CIRCUIT  
The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size;...
US20060281241 CMOS fabrication  
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region....
US20070262476 Method for providing STI structures with high coupling ratio in integrated circuit manufacturing  
A process for manufacturing an integrated circuit using shallow trench isolation (STI) includes a 2-step nitride removal process which, when combined with a nitride pull-back step provides, in a...
US20090289300 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME  
First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of...
US20070037333 Work function separation for fully silicided gates  
Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal is added to a first region of polysilicon overlying a dielectric that is on a...
US20090057742 CMOS VARACTOR  
A varactor and method of fabricating the varactor. The varactor includes a silicon body in a silicon layer of an SOI substrate; a polysilicon electrode comprising a gate region and a plate region...
US20090101972 PROCESS FOR FABRICATING A FIELD-EFFECT TRANSISTOR WITH DOPING SEGREGATION USED IN SOURCE AND/OR DRAIN  
Source and/or drain regions of a transistor are first doped with an appropriate dopant and a metal is subsequently deposited. After heating, a silicide will displace the dopant, creating an...
US20100075476 SEMICONDUCTOR DEVICE FABRICATION METHOD  
A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns...
US20120112290 CONTROLLED CONTACT FORMATION PROCESS  
A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a...
US20120320477 DEVICE FOR DETECTING AN ATTACK IN AN INTEGRATED CIRCUIT CHIP  
An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a...
US20120139053 Replacement Gate Devices With Barrier Metal For Simultaneous Processing  
A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a...
US20070257303 Transistor and method for forming the same  
A deep source/drain region and a source/drain extension region may be formed in a semiconductor substrate adjacent to a gate electrode. A first silicide layer may be formed on the source/drain...
US20090298244 Mobility Enhanced FET Devices  
NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first...
US20090230475 FIELD EFFECT STRUCTURE INCLUDING CARBON ALLOYED CHANNEL REGION AND SOURCE/DRAIN REGION NOT CARBON ALLOYED  
A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device structure. The field effect device structure includes a gate electrode located over...
US20120045873 Methods of Forming CMOS Transistors Using Tensile Stress Layers and Hydrogen Plasma Treatment  
Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen...
US20090065872 FULL SILICIDE GATE FOR CMOS  
A method is provided for fabricating an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”) in which the NFET and PFET are formed after which a protective hard...
US20080036006 Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same  
A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS...
US20150015336 CMOS CASCODE POWER CELLS  
A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a...
US20150076623 METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME  
A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the...