Matches 451 - 480 out of 480 < 1 2 3 4 5 6 7 8 9 10


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US20140091397 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THEREOF  
It is therefore an object of the present invention to provide a method in which, in a semiconductor integrated circuit device, a plurality of transistors having wide-rangingly different Ioff...
US20140091392 SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE  
There is provided a semiconductor device including a first channel-type first MISFET formed and a second channel-type second MISFET: a first source and a first drain of the first MISFET and a...
US20140030859 METHOD OF MAKING A WIRE-BASED SEMICONDUCTOR DEVICE  
In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of...
US20140021558 Dummy Gate for a High Voltage Transistor Device  
The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped...
US20140008730 Complementary Metal-Oxide-Semiconductor Device Comprising Silicon and Germanium and Method for Manufacturing Thereof  
Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a...
US20130341726 MOS TRANSISTOR, FORMATION METHOD THEREOF, AND SRAM MEMORY CELL CIRCUIT  
Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first...
US20130285152 FINFET WITH ENHANCED EMBEDDED STRESSOR  
A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and...
US20130149820 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
A method for manufacturing a semiconductor device includes providing a substrate having a first transistor device and a second transistor device formed thereon; forming a patterned stress film...
US20130122672 SEMICONDUCTOR DEVICE AND STRUCTURE  
A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including:...
US20130115743 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME  
A method for forming a semiconductor device is provided, wherein a step of forming an S/D region comprises: determining an interface region comprising an active region of a partial width abutting...
US20130105904 RADIATION HARDENED INTEGRATED CIRCUIT  
A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried...
US20130069123 CMOS SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS  
Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming first doped stressor regions in a first region of semiconductor material,...
US20130029464 METHODS FOR FABRICATING INTEGRATED CIRCUITS USING NON-OXIDIZING RESIST REMOVAL  
Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a...
US20130015497 SOURCE/DRAIN REGION, CONTACT HOLE AND METHOD FOR FORMING THE SAME  
An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first...
US20120309143 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first...
US20120292637 Dual Cavity Etch for Embedded Stressor Regions  
Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed...
US20120223391 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial...
US20120181618 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact...
US20120138953 STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs  
A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well...
US20120126332 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME  
The invention provides a semiconductor device, including: a semiconductor base, on an insulation layer; source/drain regions abutting opposite first sides of the semiconductor base; and gates at...
US20120126330 Enhanced Thin Film Field Effect Transistor Integration into Back End of Line  
A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back...
US20120115291 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE  
A semiconductor device includes a first MISFET having a first conduction type channel and formed on a semiconductor substrate; a second MISFET having a second conduction type channel and formed on...
US20120061761 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES  
Logic transistors (MOSFETs, MISFETs) in core portions of integrated circuits can be microminiaturized by scaling operating voltage as their generation advances. However, since transistors...
US20120058609 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES  
A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the...
US20110309451 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A manufacturing method of a semiconductor device includes: forming a first gate insulating film on a semiconductor substrate in first and second regions in an active area; forming first gate...
US20110275185 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE  
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and...
US20110269276 METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES  
In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device...
US20110186926 Semiconductor device having a lightly doped semiconductor gate and method for fabricating same  
According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor...
US20110089496 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD  
The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an...
US20110031556 FIN INTERCONNECTS FOR MULTIGATE FET CIRCUIT BLOCKS  
In an embodiment, an apparatus includes a first field effect transistor including a first source contact region, a first drain contact region and a first plurality of fins overlying a substrate, a...

Matches 451 - 480 out of 480 < 1 2 3 4 5 6 7 8 9 10