Applications in Class 438/197

Matches 1 - 50 out of 578

Match	Document	Document Title
1	US20110186915	REPLACEMENT GATE APPROACH BASED ON A REVERSE OFFSET SPACER APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION In a replacement gate approach, a spacer may be formed in the gate opening after the removal of the placeholder material, thereby providing a superior cross-sectional shape upon forming any...
2	US20110266626	GATE DEPLETION DRAIN EXTENDED MOS TRANSISTOR A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and...
3	US20130023093	RECESSED CONTACT FOR MULTI-GATE FET OPTIMIZING SERIES RESISTANCE A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h1); forming a...
4	US20120142150	METHOD FOR FORMING METAL GATE AND MOS TRANSISTOR The invention provides a method for forming a metal gate and a method for forming a MOS transistor. The method for forming a metal gate includes: providing a substrate; forming a sacrificial oxide...
5	US20080179638	GAP FILL FOR UNDERLAPPED DUAL STRESS LINERS A gap fill nitride is formed in an underlapping region between a first semiconductor area with a first stress liner and a second semiconductor area with a second stress liner without plugging other...
6	US20110306170	Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process A method for forming an embedded SiGe (eSiGe) PMOS transistor (102) with improved PMOS poly gate (108) doping concentration without increasing mask count and causing S/D overrun issue. After gate...
7	US20120003798	REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
8	US20090174008	METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to...
9	US20080048272	SILICIDATION MONITORING PATTERN FOR USE IN SEMICONDUCTOR MANUFACTURING PROCESS A silicidation monitoring pattern may electrically measure resistance of a polygate line after silicidation to measure open and/or short-circuiting of the polygate line. A silicidation monitoring...
10	US20080048271	STRUCTURE AND METHOD TO USE LOW k STRESS LINER TO REDUCE PARASITIC CAPACITANCE A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in...
11	US20090321855	Boundaries with elevated deuterium levels A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium.
12	US20130032901	FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a...
13	US20050077553	Methods of forming multi fin FETs using sacrificial fins and devices so formed Methods of forming multi fin Field Effect Transistors (FET) can include forming a first fin having opposing sidewalls protruding from a substrate and epitaxially growing second fins on the opposing...
14	US20090236670	Semiconductor Device and a Manufacturing Process Thereof A semiconductor device has a plurality of drain metal blocks, a plurality of source metal blocks, a plurality of polysilicon strips, a first source metal strip, a first drain metal strip, and a...
15	US20120098075	INTEGRATED ELECTRONIC DEVICE FOR DETECTING MOLECULES AND METHOD OF MANUFACTURE THEREOF An integrated electronic device for detecting gases or biological molecules having a microchip comprising integrated electronics manufactured by the CMOS process. The microchip includes a...
16	US20070004116	Trenched MOSFET termination with tungsten plug structures A metal oxide semiconductor field effect transistor (MOSFET) device includes a termination area. The termination area has a trenched gate runner electrically connected to a trenched gate of said...
17	US20090309162	SEMICONDUCTOR DEVICE HAVING DIFFERENT FIN WIDTHS A semiconductor device includes at least one source region and at least one drain region. A plurality of fins extend between a source region and a drain region, wherein at least one fin has a...
18	US20070196988	Poly pre-doping anneals for improved gate profiles A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94)...
19	US20110097858	Transition metal alloys for use as a gate electrode and devices incorporating these alloys Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or...
20	US20090042346	Electrolyte pattern and method for manufacturing an electrolyte pattern A method for manufacturing a gel electrolyte pattern is disclosed, the method comprising depositing an electrolyte precursor by inkjet printing onto a gelling agent layer. A gel electrolyte pattern...
21	US20080261358	Manufacture of Lateral Semiconductor Devices A method of manufacturing a lateral semiconductor device comprising a semiconductor body (2) having top and bottom major surfaces (2a, 2b), the body including a drain drift region (6a) of a first...
22	US20120256167	GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the...
23	US20120056249	INTERLAYER FOR ELECTRONIC DEVICES Embodiments in accordance with the present invention provide for the use of polycycloolefins in electronic devices and more specifically to the use of such polycycloolefins as interlayers applied...
24	US20070224748	SEMICONDUCTOR BODY COMPRISING A TRANSISTOR STRUCTURE AND METHOD FOR PRODUCING A TRANSISTOR STRUCTURE A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried...
25	US20110241126	RF CMOS TRANSISTOR DESIGN An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source...
26	US20050250272	Biosensor performance enhancement features and designs Isolation of semiconductor based biosensors is described. The present invention is directed to prevention of undesirable influences including, but not limited to, chip leakage current. Several...
27	US20110210403	NOVEL STRUCTURES AND METHODS TO STOP CONTACT METAL FROM EXTRUDING INTO REPLACEMENT GATES The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these...
28	US20100090269	TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device....
29	US20120161202	JUNCTIONLESS ACCUMULATION-MODE DEVICES ON PROMINENT ARCHITECTURES, AND METHODS OF MAKING SAME A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of...
30	US20110230021	Inverter, method of manufacturing the same, and logic circuit including the inverter Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different...
31	US20090166686	Edge-Contacted Vertical Carbon Nanotube Transistor A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench.
32	US20080272361	High Density Nanotube Devices Carbon-nanotube-based devices or nanowire-based devices are formed in multiple layers to obtain higher density of such devices. The layers may be all similar such as all carbon-nanotube-based...
33	US20120132998	Replacement Metal Gate Structures Providing Independent Control On Work Function and Gate Leakage Current The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided...
34	US20090108305	SEMICONDUCTOR HAVING A CORNER COMPENSATION FEATURE AND METHOD A semiconductor device includes an active semiconductor material. A transistor gate overlies a first portion of the active semiconductor material. A second portion intersects the first portion at a...
35	US20050156208	Device having multiple silicide types and a method for its fabrication Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and...
36	US20120132967	THROUGH SILICON VIA AND METHOD OF FABRICATING SAME A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the...
37	US20110024801	TRANSISTORS HAVING A COMPOSITE STRAIN STRUCTURE, INTEGRATED CIRCUITS, AND FABRICATION METHODS THEREOF A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite...
38	US20110095381	Gate structure and method for making same A MOS transistor having its gate successively comprising an insulating layer, a metal silicide layer, a layer of a conductive encapsulation material, and a polysilicon layer.
39	US20110095367	ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the...
40	US20120228679	METHOD FOR PROTECTING A GATE STRUCTURE DURING CONTACT FORMATION Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes...
41	US20080185650	FinFET for device characterization A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a...
42	US20120025927	RF ISOLATION SWITCH CIRCUIT In a first aspect, an RF switch includes a main transistor and a gate-to-source shorting circuit. When the RF switch is turned off, the gate-to-source shorting circuit is turned on to short the...
43	US20080099752	Carbon filament memory and fabrication method An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory...
44	US20060252191	Methodology for deposition of doped SEG for raised source/drain regions A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source...
45	US20060246645	A MOS Transistor with a Three-Step Source/Drain Implant A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of a separate ion implant step. The combination of the three...
46	US20080277745	FIN FILLED EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME A fin field effect transistor and method of forming the same. The fin field effect transistor comprises a semiconductor substrate having a fin structure and between two trenches with top portions...
47	US20100029050	STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor...
48	US20100001787	DYNAMICALLY-DRIVEN DEEP N-WELL CIRCUIT A circuit includes an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, and a first well switch configured to selectively...
49	US20130062669	SILICIDE FORMATION AND ASSOCIATED DEVICES Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate...
50	US20100163847	QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel...

Matches 1 - 50 out of 578

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