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US20150060947 Transistor with Diamond Gate  
A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond...
US20130214333 JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS  
An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first terminal (200), a first power supply terminal (Vdd), and a second power supply terminal (Vss). The...
US20140131775 VERTICAL GaN JFET WITH LOW GATE-DRAIN CAPACITANCE AND HIGH GATE-SOURCE CAPACITANCE  
An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type,...
US20120104467 SELF-ALIGNED CONTACT STRUCTURE TRENCH JFET  
According to one embodiment, a self-aligned trench structure junction gate field-effect transistor (JFET) includes a silicon substrate, two or more trenches having a P-type polysilicon gate region...
US20130001654 MASK-BASED SILICIDATION FOR FEOL DEFECTIVITY REDUCTION AND YIELD BOOST  
A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate...
US20090224290 Two-way Halo Implant  
A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion...
US20140138624 VERTICAL STACKING OF GRAPHENE IN A FIELD-EFFECT TRANSISTOR  
A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene...
US20130049076 POWER DEVICE WITH INTEGRATED SCHOTTKY DIODE AND METHOD FOR MAKING THE SAME  
The present invention discloses a power device with integrated power transistor and Schottky diode and a method for making the same. The power device comprises a power transistor having a drain...
US20110256674 Two-way Halo Implant  
A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion...
US20150200662 Monolithically Integrated Cascode Switches  
Disclosed inventions are directed to advanced high-voltage switches with improved performance characteristics, increased reliability, and better compatibility with conventional gate drivers. The...
US20090166675 STRAIN ENGINEERING IN SEMICONDUCTOR COMPONENTS  
This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the...
US20120104468 FABRICATING HIGH VOLTAGE TRANSISTORS IN A LOW VOLTAGE PROCESS  
Fabricating high voltage transistors includes forming a buried p-type implant on a p-substrate for each transistor, the transistor having a source side and a drain side, wherein the p-type implant...
US20140264360 TRANSISTOR WITH CHARGE ENHANCED FIELD PLATE STRUCTURE AND METHOD  
Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode...
US20090032848 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SAME  
A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one...
US20100090260 Integrated circuit layout pattern for cross-coupled circuits  
A circuit 32 is provided comprising a first diffusion region 34 and a parallel second diffusion region 36. A sequence of N gate layers 40, 42, 46 is provided with a first and an Nth of these gate...
US20110269275 Static Random Access Memory (SRAM) Cell and Method for Forming Same  
An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell...
US20100019289 Junction Field Effect Transistor Using Silicide Connection Regions and Method of Fabrication  
A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain...
US20080054312 Junction field effect transistor and production method for the same  
A junction field effect transistor of the present invention includes: a first conductivity type semiconductor substrate; a second conductivity type epitaxial layer formed on the semiconductor...
US20130168741 COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR DEVICE AND ITS GATE-LAST FABRICATION METHOD  
The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy...
US20100302810 VOLTAGE CONVERTERS WITH INTEGRATED LOW POWER LEAKER DEVICE AND ASSOCIATED METHODS  
Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first...
US20130193491 Field Controlled Diode with Positively Biased Gate  
An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well...
US20110101423 JUNCTION FIELD EFFECT TRANSISTOR  
A field effect transistor having a drain, a gate and a source, where the drain and source are formed by semiconductor regions of a first type, and in which a further doped region is provided...
US20110143505 METHOD FOR FABRICATING FIELD EFFECT TRANSISTOR  
Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on...
US20080067560 High Voltage Depletion Layer Field Effect Transistor  
In a high voltage junction field effect transistor comprising a first well (11) of a first conductivity type in a substrate (10) of a second conductivity type, comprising a source (14) and a drain...
US20060292771 High voltage depletion FET employing a channel stopping implant  
A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well...
US20120187458 Asymmetric High-Voltage JFET and Manufacturing Process  
A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a...
US20080272408 ACTIVE AREA JUNCTION ISOLATION STRUCTURE AND JUNCTION ISOLATED TRANSISTORS INCLUDING IGFET, JFET AND MOS TRANSISTORS AND METHOD FOR MAKING  
Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with...
US20100019249 JFET Devices with Increased Barrier Height and Methods of Making Same  
Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors...
US20110212583 Method For Providing Semiconductors Having Self-Aligned Ion Implant  
A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide...
US20080128762 Junction isolated poly-silicon gate JFET  
An integrated Junction Field Effect Transistor is disclosed which is much smaller and much less expensive to fabricate because it does not use Shallow Trench Isolation or field oxide in the...
US20090212330 METHOD OF FABRICATING A BURIED-GATE SEMICONDUCTOR DEVICE AND CORRESPONDING INTEGRATED CIRCUIT  
A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate...
US20070278539 Junction field effect transistor and method for manufacture  
A semiconductor device is described that operates as an improved junction field effect transistor (JFET). A bipolar transistor with a collector region, a base region, an emitter region, a first...
US20080272401 Inverted Junction Field Effect Transistor and Method of Forming Thereof  
A junction field effect transistor includes a substrate and a well region on the substrate. A channel region lies in the well region. A source region lies in the channel region. A drain region...
US20080093635 Junction Fet and Method of Manufacturing the Same  
A shallow channel region is selectively formed by ion implantation and diffusion. Since the channel region forms pn junctions with a p type semiconductor layer having a relatively low impurity...
US20140363937 POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF  
Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a...
US20110198669 TRANSISTOR AND METHOD FOR FABRICATING THE SAME  
The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode...
US20140197466 N-CHANNEL METAL-OXIDE FIELD EFFECT TRANSISTOR WITH EMBEDDED HIGH VOLTAGE JUNCTION GATE FIELD-EFFECT TRANSISTOR  
A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET...
US20080258182 Bicmos Compatible Jfet Device and Method of Manufacturing Same  
A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device,...
US20100097853 Jeet memory cell  
A memory cell (FIG. 6A) compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory cell includes a first junction field effect...
US20090302356 SEMICONDUCTOR DEVICE PREVENTING FLOATING BODY EFFECT IN A PERIPHERAL REGION THEREOF AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device having a cell region and a peripheral region includes an silicon on insulator (SOI) substrate having a stack structure of a silicon substrate, a buried insulation layer, and...
US20070072352 Insulated gate field effect transistor and manufacturing method thereof  
A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage...
US20110101424 JUNCTION FIELD EFFECT TRANSISTOR  
A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the...
US20120305943 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME  
A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift...
US20140264476 JUNCTION FET SEMICONDUCTOR DEVICE WITH DUMMY MASK STRUCTURES FOR IMPROVED DIMENSION CONTROL AND METHOD FOR FORMING THE SAME  
A method for simultaneously forming JFET devices and MOSFET devices on a substrate includes using gate structures which serve as active gate structures in the MOSFET region, as dummy gate...
US20100163934 METHOD FOR FABRICATING A JUNCTION FIELD EFFECT TRANSISTOR AND THE JUNCTION FIELD EFFECT TRANSISTOR ITSELF  
A method for fabricating a junction field effect transistor includes the steps of the type I semiconductor at the base thereof being doped with the type II semiconductor to form a type II well...
US20110227093 FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME  
The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of...
US20100171118 Junction Field-Effect Transistor Having Insulator-Isolated Source/Drain Regions and Fabrication Method Therefor  
Junction field-effect transistors (JFETs) having insulator-isolated source/drain regions and fabrication methods therefor are disclosed here. In SOI JFETs and bulk silicon JFETs having junction...
US20150060957 THREE-DIMENSIONAL GATE-WRAP-AROUND FIELD-EFFECT TRANSISTOR  
A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with...
US20120074896 Semiconductor Device Die with Integrated MOSFET and Low Forward Voltage Diode-Connected Enhancement Mode JFET and Method  
A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity....
US20100244104 COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A compound semiconductor device includes a compound semiconductor laminated structure; a source electrode, a drain electrode, and a gate electrode formed over the compound semiconductor laminated...

Matches 1 - 50 out of 74 1 2 >