Matches 1 - 48 out of 48
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US20090309098 INTERCONNECTION OF ELECTRONIC DEVICES WITH RAISED LEADS  
An embodiment of a process of manufacturing an interconnection element for contacting electronic devices is proposed. The process starts with the step of forming a plurality of leads on a main...
US20090289253 Semiconductor Wafer and Method of Forming Sacrificial Bump Pad for Wafer Probing During Wafer Sort Test  
A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in...
US20090280584 WAFER PROCESSING  
Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a number of trenches of a particular...
US20090258447 METHOD OF DETECTING HEAVY METAL IN SEMICONDUCTOR SUBSTRATE  
A method of detecting heavy metal in a semiconductor substrate, includes: a gate oxide film forming step of forming an organic oxide film by spin coating or a sol-gel process, and forming a...
US20090256149 Structure for Measuring Body Pinch Resistance of High Density Trench MOSFET Array  
A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench...
US20090239317 Method and jig structure for positioning bare dice  
A method and jig structure for positioning bare dice is disclosed. The jig structure for positioning at least one bare dice includes a trap having at least one positioning groove wherein the depth...
US20090184316 Method to extract gate to source/drain and overlap capacitances and test key structure therefor  
A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key...
US20090166618 TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS  
By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced...
US20090160470 SEMICONDUCTOR AND METHOD  
A semiconductor and method is disclosed. One embodiment includes a detector arrangement to detect the position of a connection element. A probe tip, the detector arrangement including first...
US20090162954 AC Impedance Spectroscopy Testing of Electrical Parametric Structures  
Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A...
US20090152543 System, Structure and Method of Providing Dynamic Optimization of Integrated Circuits Using a Non-Contact Method of Selection, and a Design Structure  
A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit...
US20090152544 DISGUISING TEST PADS IN A SEMICONDUCTOR PACKAGE  
A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical...
US20090152545 Feature Dimension Measurement  
A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The...
US20090140246 METHOD AND TEST STRUCTURE FOR MONITORING CMP PROCESSES IN METALLIZATION LAYERS OF SEMICONDUCTOR DEVICES  
By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer...
US20090140244 SEMICONDUCTOR DEVICE INCLUDING A DIE REGION DESIGNED FOR ALUMINUM-FREE SOLDER BUMP CONNECTION AND A TEST STRUCTURE DESIGNED FOR ALUMINUM-FREE WIRE BONDING  
In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond...
US20090114913 TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES  
A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer...
US20090098668 Method and Apparatus to Facilitate Testing of Printed Semiconductor Devices  
A printing platform receives ( 102 ) (preferably in-line with a semiconductor device printing process ( 101 )) a substrate having at least one semiconductor device printed thereon and further...
US20090083592 SEMICONDCUTOR DEVICE, MEMORY SYSTEM AND CONTROL METHOD OF THE SEMICONDUCTOR DEVICE  
A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a...
US20090068772 ACROSS RETICLE VARIATION MODELING AND RELATED RETICLE  
Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying...
US20090058456 MANUFACTURING SYSTEM, MANUFACTURING METHOD, MANAGING APPARATUS, MANAGING METHOD AND COMPUTER READABLE MEDIUM  
There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing...
US20090033350 Element Substrate, Inspecting Method, and Manufacturing Method of Semiconductor Device  
A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a...
US20090029491 METHOD OF INSPECTING DEFECT OF SEMICONDUCTOR DEVICE  
A method of inspecting defects in a semiconductor device includes forming a test pattern in a scribe lane region of a semiconductor substrate. The test pattern includes a second conductive layer...
US20090014718 TEST ELEMENT GROUP FOR MONITORING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A test element group for monitoring leakage current in a semiconductor device and a method of manufacturing the same are disclosed. The test element group for monitoring leakage current in a...
US20090001366 Wafer Arrangement and Method for Manufacturing a Wafer Arrangement  
A wafer arrangement in accordance with an embodiment of the invention includes a wafer having a plurality of dice, wherein at least some of the dice have a first connection, and at least one...
US20080286888 TEST STRUCTURES AND METHODOLOGY FOR DETECTING HOT DEFECTS  
Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at...
US20080258260 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed...
US20080237586 Semiconductor Integrated Test Structures For Electron Beam Inspection of Semiconductor Wafers  
Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions...
US20080224134 Test Structures for Identifying an Allowable Process Margin for Integrated Circuits and Related Methods  
A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines...
US20080217613 POSITIONAL OFFSET MEASUREMENT PATTERN UNIT FEATURING VIA-PLUG AND INTERCONNECTIONS, AND METHOD USING SUCH POSITIONAL OFFSET MEASUREMENT PATTERN UNIT  
In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be...
US20080206908 Semiconductor device test structures and methods  
Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive...
US20080203388 Apparatus and method for detection of edge damages  
Embodiments of the invention enable detection of edge damages in semiconductor devices. To this purpose, one or more continuity structures may be provided, where each structure comprises an...
US20080197353 SEMICONDUCTOR DEVICE FOR WHICH ELECTRICAL TEST IS PERFORMED WHILE PROBE IS IN CONTACT WITH CONDUCTIVE PAD  
A semiconductor device that comprises a conductive pad that is provided on the insulating film and that is obtained by forming a main conductive film and a surface conductive film harder than the...
US20080185584 Semiconductor device test structures and methods  
Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line...
US20080185581 Silicon-on-insulator ("SOI") transistor test structure for measuring body-effect  
According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor...
US20080185582 PORTABLE MEMORY DEVICES  
Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the...
US20080173868 METHOD AND RESULTING STRUCTURE FOR FABRICATING TEST KEY STRUCTURES IN DRAM STRUCTURES  
A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of...
US20080169466 Test Cells for semiconductor yield improvement  
A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially...
US20080149926 SEMICONDUCTOR DEVICE HAVING TEST PATTERN FOR MEASURING EPITAXIAL PATTERN SHIFT AND METHOD FOR FABRICATING THE SAME  
A semiconductor device having a test pattern for measuring epitaxial pattern shift is provided. The test pattern includes a semiconductor substrate having a first pattern formed therein; a first...
US20080145958 MONITORING OF ELECTROSTATIC DISCHARGE (ESD) EVENTS DURING SEMICONDUCTOR MANUFACTURE USING ESD SENSITIVE RESISTORS  
A monitor semiconductor chip that incorporates ESD sensitive resistors is subjected to the same steps in a semiconductor manufacturing process to which functional semiconductor chips are subjected....
US20080135841 SEMICONDUCTOR WAFER, METHOD OF MANUFACTURING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR CHIP  
A semiconductor wafer 10 has a plurality of semiconductor chip areas 10 a and a scribe area 10 b , each of the semiconductor chip areas 10 a having semiconductor elements and electrode pads...
US20080128692 Multi-purpose poly edge test structure  
A test structure in accordance with the present invention allows for testing of both V bd TDDB, and leakage current between adjacent gate features. The test structure comprises a plurality of...
US20080131983 Method for forming post passivation Au layer with clean surface  
A method for fabricating and testing a wafer includes forming metal traces with metal pads, wherein forming the metal traces include forming a TiW layer on a passivation layer and on pads, next...
US20080128693 Reliability test structure for multilevel interconnect  
Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An...
US20080105964 Substrate, semiconductor device using the same, method for inspecting semiconductor device, and method for manufacturing semiconductor device  
A substrate including therein a plurality of conductor layers laminated via insulating layers, the substrate mounting at least one semiconductor integrated circuit, wherein the substrate includes a...
US20080090314 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME  
It is in offering the technology which can solve the problem actualized in connection with the narrowing of a pitch of a bump electrode. Concretely, even if it is a case where the contact position...
US20080067619 Stress sensor for in-situ measurement of package-induced stress in semiconductor devices  
A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon...
US20080056044 Semiconductor device and fabrication method thereof  
The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit for recording a set value of a back bias potential to be...
US20080038849 Evaluation method of fine pattern, manufacturing method of device having the fine pattern  
An evaluation method includes the steps of forming a dummy pattern having a patterned part with the same critical dimension as a minimum critical dimension of an actual device having a fine pattern...
Matches 1 - 48 out of 48