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US20090057780 FINFET STRUCTURE INCLUDING MULTIPLE SEMICONDUCTOR FIN CHANNEL HEIGHTS  
A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due...
US20120190156 RECESSED GATE CHANNEL WITH LOW Vt CORNER  
A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate...
US20120161144 POLYSILICON THIN FILM TRANSISTOR HAVING TRENCH TYPE COPPER BOTTOM GATE STRUCTURE AND METHOD OF MAKING THE SAME  
Provided is a polysilicon thin film transistor having a trench type bottom gate structure using copper and a method of making the same. The polysilicon thin film transistor includes: a transparent...
US20140027818 Gate Recessed FDSOI Transistor with Sandwich of Active and Etch Control Layers  
The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and...
US20120193678 FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET  
Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a...
US20110303950 FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET  
Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a...
US20140103307 VERTICAL THIN-FILM TRANSISTOR STRUCTURE OF DISPLAY PANEL AND METHOD OF FABRICATING THE SAME  
A vertical thin-film transistor structure includes a substrate, a source electrode, an insulation layer, a drain electrode, two first channel layers, a gate insulation layer and a gate electrode,...
US20110242464 INSULATED GATE TRANSISTOR, ACTIVE MATRIX SUBSTRATE, LIQUID CRYSTAL DISPLAY DEVICE, AND METHOD FOR PRODUCING THE SAME  
According to the insulated gate transistor, a gate electrode (11A) is provided on a main surface of a glass substrate (2); a first part of an insulating layer (gate insulating layer (30) and...
US20140134808 RECESSED GATE FIELD EFFECT TRANSISTOR  
A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority...
US20130270568 THIN FILM TRANSISTOR  
Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer...
US20070202638 Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device  
A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region...
US20130122665 Method of Manufacturing a Thin Box Metal Backgate Extremely Thin SOI Device  
SOI structures with silicon layers less than 20 nm thick are used to form ETSOI semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride...
US20080102569 Method of fabricating vertical body-contacted SOI transistor  
A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal...
US20140264347 TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES BASED ON AN AMORPHIZATION PROCESS AND A HEAT TREATMENT  
When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an...
US20110220897 ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY AND FABRICATION METHOD THEREOF  
An array substrate of a liquid crystal display and a method of fabrication for the same are disclosed. The method of fabrication includes: forming a gate electrode on a first region of a...
US20110240987 THIN FILM TRANSISTOR, AND METHOD OF MANUFACTURING THE SAME  
A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a first gate electrode and an active layer including a crystalline oxide semiconductor...
US20120007180 FinFET with novel body contact for multiple Vt applications  
FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate...
US20110149656 MULTI-CELL VERTICAL MEMORY NODES  
Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel...
US20120100673 Cross OD FinFET Patterning  
A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask;...
US20090001352 Non-Volatile Memory Device, Method of Manufacturing the Same, and Semiconductor Package  
Provided is a non-volatile memory device that can be highly integrated and may have a high reliability. Some embodiments of the non-volatile memory device include a first doping layer having a...
US20110193076 THIN FILM TRANSISTOR PANEL AND FABRICATING METHOD THEREOF  
A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an...
US20110143504 THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME  
A method of fabricating a liquid crystal display device includes forming a gate electrode; forming a gate insulator on the gate electrode, an active layer on the gate insulator, and an etch...
US20090045458 MOS TRANSISTORS FOR THIN SOI INTEGRATION AND METHODS FOR FABRICATING THE SAME  
MOS transistors for thin SOI integration and methods for fabricating such MOS transistors are provided. One exemplary method includes the steps of providing a silicon layer overlying a buried...
US20130084681 PRODUCING A VERTICAL TRANSISTOR INCLUDING REENTRANT PROFILE  
Producing a vertical transistor includes providing a substrate including a gate material layer stack with a reentrant profile. A patterned deposition inhibiting material is deposited over a...
US20150255579 VTFT FORMATION USING SELECTIVE AREA DEPOSITION  
A method of producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal insulating material layer is formed on the...
US20140054679 DOPING A NON-PLANAR SEMICONDUCTOR DEVICE  
In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar...
US20120168757 Transistors, Methods Of Manufacturing The Same And Electronic Devices Including Transistors  
A transistor includes a channel layer disposed above a gate and including an oxide semiconductor. A source electrode contacts a first end portion of the channel layer, and a drain electrode...
US20110101302 WAFER-SCALE FABRICATION OF SEPARATED CARBON NANOTUBE THIN-FILM TRANSISTORS  
Methods, materials, systems and apparatus are described for depositing a separated nanotube networks, and fabricating, separated nanotube thin-film transistors and N-type separated nanotube...
US20150255583 FABRICATING VTFT WITH POLYMER CORE  
Fabricating a vertical transistor includes providing a structural polymer layer on a substrate. A patterned inorganic thin film is formed on the structural polymer layer, leaving exposed portions...
US20130307513 HIGH VOLTAGE FIELD EFFECT TRANSISTORS  
Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a...
US20150249112 Vertical Thin Film Transistors In Non-Volatile Storage Systems  
Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The...
US20110291096 ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME  
A method of fabricating an array substrate and a display device including the array substrate are discussed. According to an embodiment, the method includes forming a gate electrode on a...
US20110263081 METHODS OF MANUFACTURING CMOS TRANSISTOR  
A method of manufacturing a CMOS transistor can be provided by forming first and second gate electrodes on a substrate and forming a gate insulation layer on the first and second gate electrodes....
US20100032728 AREA EFFICIENT 3D INTEGRATION OF LOW NOISE JFET AND MOS IN LINEAR BIPOLAR CMOS PROCESS  
Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically...
US20150236145 SEMICONDUCTOR STRUCTURES AND METHODS FOR MULTI-LEVEL BAND GAP ENERGY OF NANOWIRE TRANSISTORS TO IMPROVE DRIVE CURRENT  
A semiconductor device is provided having a channel formed from a nanowire with multi-level band gap energy. The semiconductor device comprises a nanowire structure formed between source and drain...
US20150206906 MEMORIES AND METHODS OF FORMING THIN-FILM TRANSISTORS USING HYDROGEN PLASMA DOPING  
Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped...
US20140203238 Wire-Last Integration Method and Structure for III-V Nanowire Devices  
In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into...
US20120147681 METHODS, DEVICES, AND SYSTEMS RELATING TO A MEMORY CELL HAVING A FLOATING BODY  
Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a...
US20100210079 PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE  
It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain...
US20100151635 VERTICAL FLOATING BODY CELL OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
A semiconductor device includes a tube-type channel formed over a semiconductor substrate. The tube-type channel is connected to first and second conductive lines. A bias electrode is formed in...
US20170092739 Method Of Forming Ultra-Thin Nanowires  
Provided is a method of forming a nanowire-based device. The method includes forming a mask layer over a substrate; forming an opening in the mask layer; growing an arsenic-based nanowire from the...
US20170040381 3D Memory Having Vertical Switches with Surround Gates and Method Thereof  
A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT...
US20160268396 MANUFACTURING METHOD FOR VERTICAL CHANNEL GATE-ALL-AROUND MOSFET BY EPITAXY PROCESSES  
A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer...
US20160155829 Transistors and Methods of Forming Transistors  
Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the...
US20160141424 THIN FILM TRANSISTOR, ARRAY SUBSTRATE, MANUFACTURING METHOD AND DISPLAY DEVICE  
A thin film transistor, an array substrate, a manufacturing method and a display device are provided. The thin film transistor includes a substrate and a gate layer, a source layer and a drain...
US20160141336 Field Effect Transistor Constructions And Memory Arrays  
In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region....
US20160141300 THREE-DIMENSIONAL MEMORY AND METHOD FOR MANUFACTURING THE SAME  
A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film transistor. The thin-film transistor has a...
US20160118479 3D UTB Transistor Using 2D-Material Channels  
A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the...
US20160118415 ARRAY SUBSTRATE, DISPLAY PANEL AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR  
An array substrate, a display panel and a method of manufacturing a thin film transistor (TFT) are provided. The array substrate includes a base substrate and a thin film transistor (TFT) formed...
US20160099329 SUSPENDED BODY FIELD EFFECT TRANSISTOR  
A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure...

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