Matches 1 - 50 out of 275 1 2 3 4 5 6 >


Match Document Document Title
US20130026466 TESTING ARCHITECTURE OF CIRCUITS INTEGRATED ON A WAFER  
An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing...
US20090167343 MINIMIZING LEAKAGE IN LOGIC DESIGNS  
Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic application where high threshold...
US20140183602 ALTERNATING TAP-CELL STRATEGY IN A STANDARD CELL LOGIC BLOCK FOR AREA REDUCTION  
An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located...
US20110156755 FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION  
Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit...
US20150252217 UNDERFILL COMPOSITION FOR ENCAPSULATING A BOND LINE  
An underfill composition for encapsulating a bond line and a method of using the underfill composition are described. Advantageously, the disclosed underfill composition in an uncured state has a...
US20120286331 INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS  
Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in...
US20110298492 Adjustable Interface Buffer Circuit Between A Programmable Logic Device And A Dedicated Device  
An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different...
US20060275956 Cross-linked carbon nanotubes  
Cross-linked carbon nanotube arrays forming a three-dimensional structure and methods of use including high thermal conductivity, high strength applications where repeated cycling is known, and...
US20140151751 DENSITY GRADIENT CELL ARRAY  
One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy...
US20090321789 Triangle two dimensional complementary patterning of pillars  
A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three...
US20100090348 Single-Sided Trench Contact Window  
An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the...
US20100261317 OFFSET NON-VOLATILE STORAGE  
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce...
US20100155783 Standard Cell Architecture and Methods with Variable Design Rules  
Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a...
US20090146189 Pads and pin-outs in three dimensional integrated circuits  
A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a memory array positioned above or...
US20070235766 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN OBLIQUE GLOBAL SIGNAL WIRING AND SEMICONDUCTOR INTEGRATED CIRCUIT WIRING METHOD  
A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell...
US20090101940 DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES  
A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell...
US20080157221 STRUCTURE OF SEMICONDUCTOR DEVICE FOR DECREASING CHIP AREA AND MANUFACTURING METHOD THEREOF  
A method of manufacturing a semiconductor device for decreasing a chip area by changing a connecting structure of pull up transistors and pull down transistors are disclosed. The semiconductor...
US20090162977 Non-Volatile Memory Fabrication And Isolation For Composite Charge Storage Structures  
Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge...
US20090026502 VIA ANTENNA FIX IN DEEP SUB-MICRON CIRCUIT DESIGNS  
A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler...
US20130154027 Memory Cell  
A memory cell and array and a method of forming a memory cell and array are disclosed. An embodiment is a memory cell comprising first and second pull-up transistors, first and second pull-down...
US20130015882 Compact and Robust Level Shifter Layout Design  
Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power...
US20120032702 HARDENED PROGRAMMABLE DEVICES  
Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used...
US20130292633 ETCH BIAS HOMOGENIZATION  
Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at...
US20060057783 Methods of forming fuses using selective etching of capping layers  
A method of forming a fuse in a semiconductor device can be provided by selectively removing an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around...
US20060087883 Anti-tamper module  
An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration...
US20090003060 High density NOR flash array architecture  
In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and...
US20150069470 INTEGRATED CIRCUIT DEVICE  
An integrated circuit device includes a plurality of basic cells that each have a first transistor pair including two p-channel transistors of a first-type and a second transistor pair including...
US20080186777 Relaxed metal pitch memory architectures  
A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and...
US20090121804 MONOLITHIC SEMICONDUCTOR MICROWAVE SWITCH ARRAY  
A microwave switch array includes a plurality of microwave slotlines, each of which is controlled by a semiconductor switch including a first PIN junction formed by a primary P-type electrode and...
US20070238225 Phase change memory with improved temperature stability  
A phase change memory may be formed using a chalcogenide material that includes selenium. The inclusion of selenium improves the heat stability of the resulting memory device. The chalcogenide may...
US20140197463 METAL-PROGRAMMABLE INTEGRATED CIRCUITS  
A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure...
US20070059867 METHOD OF MANUFACTURING AN OPTICAL MODULE  
Manufacturing an optical module includes providing a frame, attaching a light-emitting diode chip and a sensor chip to the frame, and forming overcoats on the light-emitting diode chip and the...
US20060172452 Detector  
A detector includes a CCD arrangement having at least one CCD, and a focusing device. The focusing device focuses spectrally separated light onto the CCD arrangement. The focusing device is...
US20090309089 Non-Volatile Memory Arrays Comprising Rail Stacks with a Shared Diode Component Portion for Diodes of Electrically Isolated Pillars  
An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells...
US20120001654 Three Dimensional Multilayer Circuit  
A three dimensional multilayer circuit (400) includes a via array (325, 330) made up of a set of first vias (325) and a set of second vias (330) and an area distributed CMOS layer (310) configured...
US20130182490 Static Random Access Memory Cell with Single-Sided Buffer and Asymmetric Construction  
Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read...
US20050148117 Method for fabricating a flash-preventing window ball grid array semiconductor package  
A flash-preventing window ball grid array semiconductor package, a method for fabricating the same, and a chip carrier used in the semiconductor package are provided. The chip carrier has a...
US20090166683 FLEXIBLE LAYOUT FOR INTEGRATED MASK-PROGRAMMABLE LOGIC DEVICES AND MANUFACTURING PROCESS THEREOF  
Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom...
US20090179184 VERTICAL SPACER ELECTRODES FOR VARIABLE-RESISTANCE MATERIAL MEMORIES AND VERTICAL SPACER VARIABLE-RESISTANCE MATERIAL MEMORY CELLS  
Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes...
US20090267044 PHASE CHANGE MEMORY DEVICE HAVING A BENT HEATER AND METHOD FOR MANUFACTURING THE SAME  
A phase change memory device includes heaters which are formed in their respective memory cells and vertically positioned stack patterns having phase change layers and top electrodes which are...
US20060091423 Layer fill for homogenous technology processing  
Spare transistors are formed in regions of a semiconductor device where functional transistors are not formed, providing uniformity in etch and polishing processes, and resulting in transistors...
US20070029575 Structure and method of measuring the capacitance  
The structure and method of measuring the capacitance comprising a first buried doped area and a heavily doped area in a semiconductor substrate. The heavily doped area is parallel to the buried...
US20100323480 MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS  
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for...
US20090040824 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device includes a plurality of a word lines. The word lines have a set of odd word lines and a set of even word lines. The odd and the even word lines are located from a first end...
US20130234210 METHOD OF MANUFACTURING METAL SILICIDE AND SEMICONDUCTOR STRUCTURE USING THE SAME  
A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization...
US20110151628 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection  
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current...
US20130171777 PROCESSING UNIT COMPRISING INTEGRATED CIRCUITS INCLUDING A COMMON CONFIGURATION OF ELECTRICAL INTERCONNECTS  
A processing unit comprises a plurality of individual integrated circuits (ICs) electrically connected to one another via a common configuration of electrical interconnects (e.g., through-silicon...
US20090309136 SEA-OF-FINS STRUCTURE OF A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION  
A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin...
US20090189194 Electrostatic Discharge (ESD) Protection Circuit Placement in Semiconductor Devices  
Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an...
US20070087484 Heating Element Of A Printhead Having Resistive Layer Over Conductive Layer  
A heating element of a printhead has a conductive layer deposited over a substrate, and a resistive layer deposited over and in electrical contact with the conductive layer.

Matches 1 - 50 out of 275 1 2 3 4 5 6 >