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US20150024549 ALIGNMENT OF INTEGRATED CIRCUIT CHIP STACK  
The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod...
US20110250722 INVERSE CHIP CONNECTOR  
A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second...
US20120184069 METHOD FOR BONDING OF CHIPS ON WAFERS  
Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically...
US20140253196 FLIP-FLOPS IN A MONOLITHIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) AND RELATED METHODS  
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed...
US20140049293 Three-Dimensional High Voltage Gate Driver Integrated Circuit  
A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side...
US20120280738 VARIABLE ATTENUATOR HAVING STACKED TRANSISTORS  
In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment...
US20150115413 Assembly of Wafer Stacks  
A method of forming a wafer stack includes providing a sub-stack comprising a first wafer and a second wafer. The sub-stack includes a first thermally-curable adhesive at an interface between the...
US20150048500 Multi-Chip Structure and Method of Forming Same  
A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer. The device further...
US20140151900 STACKED PACKAGING USING RECONSTITUTED WAFERS  
An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The...
US20150061110 STACKED CHIP LAYOUT AND METHOD OF MAKING THE SAME  
A stacked chip layout includes a central processing chip has a first area and a first active circuit block over the central processing chip, the first active circuit block has a second area. The...
US20090325345 Method of manufacturing layered chip package  
A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of...
US20080315380 INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING PERIMETER PADDLE  
An integrated circuit package system comprising: forming a paddle having a hole and an external interconnect; mounting an integrated circuit device having an active side to the paddle with the...
US20140061947 CHIP STACK STRUCTURE AND MANUFACTURING METHOD THEREOF  
A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a first chip, a second chip and a vertical conductive line. The second chip is disposed...
US20090096077 Tenon-and-mortise packaging structure  
A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least...
US20140203428 CHIP STACK WITH ELECTRICALLY INSULATING WALLS  
A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area...
US20130234320 CHIP STACK STRUCTURE AND METHOD FOR FABRICATING THE SAME  
A chip stack structure taking a wafer as a stacking base and stacking chips thereon is provided. The chip stack structure is capable of achieving high density electrode bonding and breaking the...
US20110215457 Dummy TSV to Improve Process Uniformity and Heat Dissipation  
In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning,...
US20130302943 DUAL-SIDE INTERCONNECTED CMOS FOR STACKED INTEGRATED CIRCUITS  
A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers...
US20110248403 Dual-Side Interconnected CMOS For Stacked Integrated Circuits  
A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers...
US20140070390 MULTI-CHIP PACKAGING STRUCTURE AND METHOD  
Disclosed are multi-chip packaging structures and methods. In one embodiment, a multi-chip packaging structure can include: (i) N chips, where N is an integer of at least two, and where an upper...
US20090283872 PACKAGE STRUCTURE OF THREE-DIMENSIONAL STACKING DICE AND METHOD FOR MANUFACTURING THE SAME  
This invention provides a package structure of three-dimensional stacking dice and its manufacturing method. This invention employs the Through-Silicon-Vias (TSVs) technology to establish vertical...
US20090166888 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD  
A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The...
US20090032969 Arrangement of Integrated Circuit Dice and Method for Fabricating Same  
An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is...
US20090189292 Integrated Circuit, Semiconductor Module and Method for Manufacturing a Semiconductor Module  
Embodiments of the invention relate to a semiconductor, a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, an integrated circuit...
US20090166885 INTEGRATED CIRCUIT PACKAGE WITH IMPROVED CONNECTIONS  
An integrated circuit package system comprising: providing an integrated circuit die; forming a top paddle over the integrated circuit die wherein the top paddle has planar dimensions smaller than...
US20140264948 Air Trench in Packages Incorporating Hybrid Bonding  
A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar...
US20120178212 WAFER-TO-WAFER STACK WITH SUPPORTING PEDESTAL  
A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer...
US20140097524 COPLANAR WAVEGUIDE FOR STACKED MULTI-CHIP SYSTEMS  
An approach for a coplanar waveguide structure in stacked multi-chip systems is provided. A method of manufacturing a semiconductor structure includes forming a first coplanar waveguide in a first...
US20090212390 INDUCTIVELY COUPLED INTEGRATED CIRCUIT AND METHODS FOR USE THEREWITH  
A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die has a second circuit and a second inductive...
US20090152702 Coupling wire to semiconductor region  
A first device has a surface and includes a micrometer-scale or smaller geometry doped semiconductor region extending along the surface. A second device has a surface opposite the surface of the...
US20080224279 VERTICAL ELECTRICAL INTERCONNECT FORMED ON SUPPORT PRIOR TO DIE MOUNT  
A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into...
US20150214208 MICROELECTRONIC ASSEMBLY HAVING A HEAT SPREADER FOR A PLURALITY OF DIE  
A method of manufacturing a microelectronic assembly (100) and a microelectronic device (4100) that include a stacked structure (101). The stacked structure includes a heat spreader (104), at...
US20110147906 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated...
US20120133057 EDGE CONNECT WAFER LEVEL STACKING  
A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at...
US20150044821 METHOD FOR FABRICATING MULTI-CHIP STACK STRUCTURE  
A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a...
US20090023247 METHOD FOR FORMING SIDE WIRINGS  
After plural semiconductor elements are stacked to form a stacked body P, side wirings are formed on the side surface of the stacked body P, thereby manufacturing a semiconductor apparatus in...
US20070132082 Copper plating connection for multi-die stack in substrate package  
An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another...
US20090273068 3-D Integrated Circuit Lateral Heat Dissipation  
By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The...
US20110101497 METHOD FOR FABRICATING A FLIP-BONDED DUAL-SUBSTRATE INDUCTOR, FLIP-BONDED DUAL-SUBSTRATE INDUCTOR, AND INTEGRATED PASSIVE DEVICE INCLUDING A FLIP-BONDED DUAL-SUBSTRATE INDUCTOR  
A flip-bonded dual-substrate inductor includes a base substrate, a first inductor body portion provided on a surface of the base substrate, a cover substrate, a second inductor body portion...
US20090261457 DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET  
A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an...
US20090001540 Stackable Package by Using Internal Stacking Modules  
A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical...
US20150187733 COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION  
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for...
US20120181698 FORMING THROUGH-SILICON-VIAS FOR MULTI-WAFER INTEGRATED CIRCUITS  
The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and...
US20080093723 Passive placement in wire-bonded microelectronics  
A microelectronic assembly includes a first microelectronic device electrically coupled with a second microelectronic device via wire bond attachment, the first microelectronic device being...
US20070182081 SPIN UNIT IN WAFER SPINNER APPARATUS AND METHOD OF REPOSITIONING SPIN UNIT  
A wafer spinner apparatus includes a main body, and a plurality of spin units disposed in the main body to open and close in a rack configuration, each spin unit including a stepping motor...
US20150262904 Package with Embedded Heat Dissipation Features  
An integrated circuit package and a method of fabrication of the same are introduced. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in...
US20070052084 High density interconnect assembly comprising stacked electronic module  
A microelectronic module is provided with one or more first conductive pads on at least one of the exterior surfaces of the module for electrical interconnection of the functionality of the module...
US20140154840 CHIP PACKAGE AND METHOD FOR FORMING THE SAME  
An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second...
US20080017966 Pillar Bump Package Technology  
A semiconductor product includes a die and leadframe included in a package made of plastic or other insulating material. The die and leadframe are dimensioned so that they overlap in at least one...
US20150235898 ELECTRONIC DEVICES UTILIZING CONTACT PADS WITH PROTRUSIONS AND METHODS FOR FABRICATION  
An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front-side vias extending from the front side into a...