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US20080128882 CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE SAME  
A chip stack package comprising an intermediate substrate having a recess, a first chip mounted in the recess, a second chip over the intermediate substrate, a package substrate formed under the...
US20070281391 Attachment method, attachment apparatus, manufacturing method of semiconductor device, and manufacturing apparatus of semiconductor device  
The invention proposes a method and an apparatus for attaching a plurality of components having different arrangement densities or arrangement intervals, which can achieve shorter takt time. An...
US20100230795 STACKED MICROELECTRONIC ASSEMBLIES HAVING VIAS EXTENDING THROUGH BOND PADS  
A stacked microelectronic assembly is provided which includes first and second stacked microelectronic elements. Each of the first and second microelectronic elements can include a conductive...
US20100127345 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES  
3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34)...
US20090039528 Wafer level stacked packages with individual chip selection  
A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like...
US20150186067 SPI INTERFACE ENHANCED FLASH CHIP AND CHIP PACKAGING METHOD  
Disclosed are an enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises...
US20150001948 DIE-TO-DIE INDUCTIVE COMMUNICATION DEVICES AND METHODS  
Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die....
US20140042601 MULTI-CHIP STACKING OF INTEGRATED CIRCUIT DEVICES USING PARTIAL DEVICE OVERLAP  
One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region...
US20130214401 System and Method for Fine Pitch PoP Structure  
A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die...
US20080315385 Array molded package-on-package having redistribution lines  
A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads...
US20150064845 METHOD OF FORMING AN INTEGRATED CIRCUIT PACKAGE  
A method of fabricating an integrated circuit package assembly comprises forming solder bumps over a first surface of a first integrated circuit package. The method also comprises forming at least...
US20100258928 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a first integrated circuit to the substrate by interconnects only along opposite sides of...
US20090004777 Stacked die semiconductor package and method of assembly  
A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality...
US20110140258 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system including: fabricating a base package substrate having component pads and stacking pads; coupling a base integrated circuit die to...
US20080265434 SEMICONDUCTOR DEVICE HAVING A SEALING RESIN AND METHOD OF MANUFACTURING THE SAME  
The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face...
US20080001305 Semiconductor device and manufacturing method of same  
In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second...
US20060012035 Method of packaging integrated circuits, and integrated circuit packages produced by the method  
A method of packaging integrated circuits is proposed in which two integrated circuits 13, 17 are provided in register on opposite sides of a single substrate 1. Electrical contacts on the each of...
US20120267791 MULTI CHIP PACKAGE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE MULTI CHIP PACKAGE  
A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through...
US20120273967 Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer  
A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by...
US20100140810 CHIP PACKAGE WITH COPLANARITY CONTROLLING FEATURE  
A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion...
US20090039524 METHODS AND APPARATUS TO SUPPORT AN OVERHANGING REGION OF A STACKED DIE  
Methods and apparatus to support an overhanging region of stacked die are disclosed. A disclosed method comprises bonding a first die onto a substrate, placing a support element on the substrate;...
US20140264946 PACKAGE-ON-PACKAGE STRUCTURE WITH REDUCED HEIGHT  
To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to...
US20100144094 Method of Forming Stacked Dies  
The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs...
US20150108615 TECHNIQUE FOR CONTROLLING POSITIONS OF STACKED DIES  
An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack...
US20110084373 INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF  
A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect...
US20090075426 Method for Fabricating Multi-Chip Stacked Package  
A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing...
US20090032927 SEMICONDUCTOR SUBSTRATES CONNECTED WITH A BALL GRID ARRAY  
A stacked module has an upper semiconductor package that includes a substrate having opposed first and second surfaces. A cavity defined in the second surface receives at least a portion of a...
US20070035002 Semiconductor device and a manufacturing method of the same  
The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on...
US20140175646 PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME  
An exemplary package substrate includes a package substrate, a first connection substrate, a first chip, a dielectric adhesive sheet, a second chip, and a second connection substrate. The package...
US20110033979 EDGE CONNECT WAFER LEVEL STACKING  
A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second...
US20100314737 Intra-Die Routing Using Back Side Redistribution Layer and Associated Method  
A semiconductor die includes: a body portion with a plurality of circuit components, a front side including electrical couplings to the plurality of circuit components, a back side having a...
US20080211078 SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING THE SAME  
A stacked semiconductor package can be formed according to principles of the present invention by stacking a plurality of semiconductor packages. A method of manufacturing the stacked...
US20100133645 METHOD FOR STACKING AND INTERCONNECTING INTEGRATED CIRCUITS  
A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material;...
US20090218671 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
In a semiconductor device of the present invention, semiconductor chips are stacked in multi-layers. Each of the semiconductor chip includes: through vias extending through a top main surface...
US20150028493 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is...
US20140225235 THREE-DIMENSIONAL (3-D) INTEGRATED CIRCUITS (3DICS) WITH GRAPHENE SHIELD, AND RELATED COMPONENTS AND METHODS  
A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3DIC. A...
US20090166834 MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING INTERPOSER  
A mountable integrated circuit package system includes: forming a base integrated circuit package system includes: providing a first substrate, and forming a package encapsulation having a cavity...
US20060255444 System and method for vertically stacking computer memory components  
System and method for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One embodiment provides a chip stack where two...
US20140206143 CHIP STACK WITH ELECTRICALLY INSULATING WALLS  
A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent...
US20120211867 SIDE-MOUNTED CONTROLLER AND METHODS FOR MAKING THE SAME  
A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a...
US20110084401 PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS AND METHOD FOR MANUFACTURING THEREOF  
A method for manufacturing a package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit...
US20110062574 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated...
US20100285635 CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE  
A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each...
US20080088001 Package on package and method thereof  
A package on package (POP) and method thereof are provided. The example POP may include a first semiconductor package including a first substrate, the first substrate being a flexible substrate...
US20140087492 Exclusion Zone for Stress-Sensitive Circuit Design  
A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are...
US20110089552 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system including: forming a top package including: providing a through silicon via interposer having a through silicon via; coupling a...
US20150187734 Packages with Die Stack Including Exposed Molding Underfill  
A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion...
US20100159643 BONDING IC DIE TO TSV WAFERS  
A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and...
US20090001600 ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE AND METHODS OF FORMING THE SAME  
An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a...
US20130026655 CHIP PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
A chip package structure includes a substrate in which a plurality of grooves are formed, an adhesive layer disposed on the substrate, and a plurality of chips attached to the adhesive layer. In...