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US20110084373 INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF  
A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect...
US20090075426 Method for Fabricating Multi-Chip Stacked Package  
A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a...
US20090032927 SEMICONDUCTOR SUBSTRATES CONNECTED WITH A BALL GRID ARRAY  
A stacked module has an upper semiconductor package that includes a substrate having opposed first and second surfaces. A cavity defined in the second surface receives at least a portion of a...
US20070035002 Semiconductor device and a manufacturing method of the same  
The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the...
US20140175646 PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME  
An exemplary package substrate includes a package substrate, a first connection substrate, a first chip, a dielectric adhesive sheet, a second chip, and a second connection substrate. The package...
US20110033979 EDGE CONNECT WAFER LEVEL STACKING  
A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second...
US20100314737 Intra-Die Routing Using Back Side Redistribution Layer and Associated Method  
A semiconductor die includes: a body portion with a plurality of circuit components, a front side including electrical couplings to the plurality of circuit components, a back side having a...
US20080211078 SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING THE SAME  
A stacked semiconductor package can be formed according to principles of the present invention by stacking a plurality of semiconductor packages. A method of manufacturing the stacked semiconductor...
US20100133645 METHOD FOR STACKING AND INTERCONNECTING INTEGRATED CIRCUITS  
A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material;...
US20090218671 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
In a semiconductor device of the present invention, semiconductor chips are stacked in multi-layers. Each of the semiconductor chip includes: through vias extending through a top main surface...
US20150028493 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is...
US20140225235 THREE-DIMENSIONAL (3-D) INTEGRATED CIRCUITS (3DICS) WITH GRAPHENE SHIELD, AND RELATED COMPONENTS AND METHODS  
A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3DIC. A...
US20090166834 MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING INTERPOSER  
A mountable integrated circuit package system includes: forming a base integrated circuit package system includes: providing a first substrate, and forming a package encapsulation having a cavity...
US20060255444 System and method for vertically stacking computer memory components  
System and method for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One embodiment provides a chip stack where two...
US20140206143 CHIP STACK WITH ELECTRICALLY INSULATING WALLS  
A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent...
US20120211867 SIDE-MOUNTED CONTROLLER AND METHODS FOR MAKING THE SAME  
A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a...
US20110084401 PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS AND METHOD FOR MANUFACTURING THEREOF  
A method for manufacturing a package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit...
US20110062574 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated...
US20100285635 CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE  
A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of...
US20080088001 Package on package and method thereof  
A package on package (POP) and method thereof are provided. The example POP may include a first semiconductor package including a first substrate, the first substrate being a flexible substrate...
US20140087492 Exclusion Zone for Stress-Sensitive Circuit Design  
A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are...
US20110089552 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system including: forming a top package including: providing a through silicon via interposer having a through silicon via; coupling a...
US20100159643 BONDING IC DIE TO TSV WAFERS  
A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and...
US20090001600 ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE AND METHODS OF FORMING THE SAME  
An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a...
US20130026655 CHIP PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
A chip package structure includes a substrate in which a plurality of grooves are formed, an adhesive layer disposed on the substrate, and a plurality of chips attached to the adhesive layer. In...
US20110298107 SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of a shielded stacked integrated circuit packaging system includes: forming a first integrated circuit structure having a first substrate and a first integrated circuit die;...
US20100320582 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an...
US20090121346 Flexible Interposer for Stacking Semiconductor Chips and Connecting Same to Substrate  
A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably about 25 to 50 μm thick, has ...
US20090026628 ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES  
A semiconductor package includes a first semiconductor chip mounted on a substrate and a second semiconductor chip mounted on top of the first semiconductor chip. A plurality of metal lines is...
US20120080782 METHOD OF MANUFACTURING LAYERED CHIP PACKAGE  
A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and...
US20090045444 INTEGRATED DEVICE AND CIRCUIT SYSTEM  
An integrated circuit, comprising a substrate stack, comprising a first substrate and a second substrate, the first substrate comprising a first contact field on a side face of the substrate stack...
US20090091042 INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE HAVING RELIEVED ACTIVE REGION  
An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond...
US20080237889 Semiconductor package, method of fabricating the same, and semiconductor package mold  
Provided is a semiconductor package, which may include a plurality of semiconductor chips to form a multi-stack semiconductor package (MSP), a method of fabricating the semiconductor package and...
US20080237589 Semiconductor device comprising circuit substrate with inspection connection pads and manufacturing method thereof  
A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof,...
US20080224305 METHOD, APPARATUS, AND SYSTEM FOR PHASE CHANGE MEMORY PACKAGING  
According to one embodiment, a die assembly is disclosed, comprising a package substrate and a plurality of stacked die on the package substrate, the plurality of stacked die including at least an...
US20080197460 PACKAGED IC DEVICE COMPRISING AN EMBEDDED FLEX CIRCUIT, AND METHODS OF MAKING SAME  
A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a...
US20060043561 Semiconductor apparatus having stacked semiconductor components  
The present invention provides an apparatus having stacked semiconductor components. Two semiconductor components (21, 26) are arranged such that their contact regions (28, 22) are opposite one...
US20140264945 STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF  
A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge...
US20130217183 STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS  
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding...
US20100044856 ELECTRONIC PACKAGE WITH A THERMAL INTERPOSER AND METHOD OF MANUFACTURING THE SAME  
An electronic package includes a die including a thermal interface material through which a primary heat flux path is enabled for conducting heat from the die, an organic substrate, and a thermal...
US20100025837 COMPOSITE SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND SPACER SHEET USED IN THE SAME, AND METHOD FOR MANUFACTURING COMPOSITE SEMICONDUCTOR DEVICE  
The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises: an upper semiconductor package which comprises a...
US20090057914 MULTIPLE CHIP SEMICONDUCTOR DEVICE  
A semiconductor device has first and second semiconductor chips comprising electronic circuit elements located at an inner part of the chip and first connection terminals located on an upper...
US20100127407 Two-sided substrateless multichip module and method of manufacturing same  
A two-sided substrateless multichip module including at least one die layer having at least one die. At least one bottomside interconnect layer is coupled to a bottom surface of the at least one...
US20090305464 Array-Processed Stacked Semiconductor Packages  
One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating...
US20080150103 Multi-Die Ic Package and Manufacturing Method  
A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of...
US20070249094 Method for fabricating multi-chip semiconductor package  
A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder...
US20100096741 Chip-Stacked Package Structure and Method for Manufacturing the Same  
A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a...
US20100047967 METHOD OF MANUFACTURING STACKED SEMICONDUCTOR PACKAGE USING IMPROVED TECHNIQUE OF FORMING THROUGH VIA  
A method of manufacturing a stacked semiconductor package using an improved technique of forming a through via in order to enable 3-dimensional vertical interconnection of stacked packages is...
US20080185703 INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES  
A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an...
US20070170571 Low profile semiconductor system having a partial-cavity substrate  
A system (100), which has an electrically insulating substrate (101) with a thickness, a first and a second surface. Electrically conductive paths (110) extend through the insulating body from the...