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US20090121346 Flexible Interposer for Stacking Semiconductor Chips and Connecting Same to Substrate  
A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably about 25 to 50 μm thick, has ...
US20090026628 ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES  
A semiconductor package includes a first semiconductor chip mounted on a substrate and a second semiconductor chip mounted on top of the first semiconductor chip. A plurality of metal lines is...
US20120080782 METHOD OF MANUFACTURING LAYERED CHIP PACKAGE  
A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and...
US20090045444 INTEGRATED DEVICE AND CIRCUIT SYSTEM  
An integrated circuit, comprising a substrate stack, comprising a first substrate and a second substrate, the first substrate comprising a first contact field on a side face of the substrate stack...
US20090091042 INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE HAVING RELIEVED ACTIVE REGION  
An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond...
US20080237889 Semiconductor package, method of fabricating the same, and semiconductor package mold  
Provided is a semiconductor package, which may include a plurality of semiconductor chips to form a multi-stack semiconductor package (MSP), a method of fabricating the semiconductor package and...
US20080237589 Semiconductor device comprising circuit substrate with inspection connection pads and manufacturing method thereof  
A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof,...
US20080224305 METHOD, APPARATUS, AND SYSTEM FOR PHASE CHANGE MEMORY PACKAGING  
According to one embodiment, a die assembly is disclosed, comprising a package substrate and a plurality of stacked die on the package substrate, the plurality of stacked die including at least an...
US20080197460 PACKAGED IC DEVICE COMPRISING AN EMBEDDED FLEX CIRCUIT, AND METHODS OF MAKING SAME  
A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a...
US20060043561 Semiconductor apparatus having stacked semiconductor components  
The present invention provides an apparatus having stacked semiconductor components. Two semiconductor components (21, 26) are arranged such that their contact regions (28, 22) are opposite one...
US20130217183 STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS  
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding...
US20100044856 ELECTRONIC PACKAGE WITH A THERMAL INTERPOSER AND METHOD OF MANUFACTURING THE SAME  
An electronic package includes a die including a thermal interface material through which a primary heat flux path is enabled for conducting heat from the die, an organic substrate, and a thermal...
US20100025837 COMPOSITE SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND SPACER SHEET USED IN THE SAME, AND METHOD FOR MANUFACTURING COMPOSITE SEMICONDUCTOR DEVICE  
The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises: an upper semiconductor package which comprises a...
US20090057914 MULTIPLE CHIP SEMICONDUCTOR DEVICE  
A semiconductor device has first and second semiconductor chips comprising electronic circuit elements located at an inner part of the chip and first connection terminals located on an upper...
US20100127407 Two-sided substrateless multichip module and method of manufacturing same  
A two-sided substrateless multichip module including at least one die layer having at least one die. At least one bottomside interconnect layer is coupled to a bottom surface of the at least one...
US20090305464 Array-Processed Stacked Semiconductor Packages  
One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating...
US20080150103 Multi-Die Ic Package and Manufacturing Method  
A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of...
US20070249094 Method for fabricating multi-chip semiconductor package  
A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder...
US20100096741 Chip-Stacked Package Structure and Method for Manufacturing the Same  
A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a...
US20100047967 METHOD OF MANUFACTURING STACKED SEMICONDUCTOR PACKAGE USING IMPROVED TECHNIQUE OF FORMING THROUGH VIA  
A method of manufacturing a stacked semiconductor package using an improved technique of forming a through via in order to enable 3-dimensional vertical interconnection of stacked packages is...
US20080185703 INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES  
A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an...
US20070170571 Low profile semiconductor system having a partial-cavity substrate  
A system (100), which has an electrically insulating substrate (101) with a thickness, a first and a second surface. Electrically conductive paths (110) extend through the insulating body from the...
US20070023886 METHOD FOR PRODUCING A CHIP ARRANGEMENT, A CHIP ARRANGEMENT AND A MULTICHIP DEVICE  
The present invention relates to a method and apparatus for producing a chip arrangement. In one embodiment, the method includes providing a first chip having an electrically operable structure, of...
US20110159639 Method for Making a Stackable Package  
The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first...
US20110115098 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION AND METHOD FOR MANUFACTURING THEREOF  
A method for manufacturing an integrated circuit package system includes: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the...
US20100032820 Stacked Memory Module  
Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed...
US20080230903 SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME  
A semiconductor chip constitutes a semiconductor device in which a plurality of semiconductor chips are laminated. The semiconductor chip includes a plurality of terminals which are to be connected...
US20080174008 Structure of Memory Card and the Method of the Same  
The present invention provides a structure of memory card comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed...
US20140015130 MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS  
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package...
US20100173454 MICROELECTRONIC PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAMES CONFIGURED FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS  
Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment...
US20080273314 PCB having embedded IC and method for manufacturing the same  
A multi-layer PCB includes a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-hole formed in the insulating layers so as to...
US20080088031 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME  
A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming...
US20130260510 3-D Integrated Circuits and Methods of Forming Thereof  
In one embodiment, a method of forming a semiconductor device includes stacking a second wafer with a first wafer and forming a through via extending through the second wafer while the second wafer...
US20110147911 STACKABLE CIRCUIT STRUCTURES AND METHODS OF FABRICATION THEREOF  
Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its...
US20100317153 Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street  
A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed the die. The trench extends to...
US20100123232 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING AN INTERNAL STRUCTURE PROTRUSION AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing an internal structure substrate having an internal structure substrate cavity; mounting an internal structure...
US20100059885 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER  
An integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and...
US20080315406 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE  
An integrated circuit package system includes a base substrate having a base substrate cavity, attaching a junction integrated circuit package over the base substrate with a portion of the junction...
US20110049694 Semiconductor Wafer-To-Wafer Bonding For Dissimilar Semiconductor Dies And/Or Wafers  
A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects...
US20100096737 STACKABLE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES  
Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality...
US20090302449 PACKAGED PRODUCTS, INCLUDING STACKED PACKAGE MODULES, AND METHODS OF FORMING SAME  
An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical...
US20080173998 CHIP ARRANGEMENT AND METHOD FOR PRODUCING A CHIP ARRANGEMENT  
A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first...
US20080150133 Semiconductor Chip Assembly And Fabrication Method Therefor  
A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is realized. This is achieved by the assembly...
US20140061951 PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME  
A method for manufacturing a package on package structure includes the step of: providing a package body comprising a first package device and a connection substrate, the first package device...
US20120043669 STACKED SEMICONDUCTOR CHIP DEVICE WITH THERMAL MANAGEMENT CIRCUIT BOARD  
A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the...
US20100320603 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING THEREOF  
A method for manufacturing an integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and...
US20090166846 PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS  
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first...
US20090146282 Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads  
A semiconductor package has a first semiconductor die mounted on a substrate. A conductive via is formed through the substrate. A first RDL is formed on a first surface of the substrate in...
US20090111217 Method of manufacturing chip-on-chip semiconductor device  
Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device...
US20120326300 LOW PROFILE PACKAGE AND METHOD  
In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer...