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US20090305464 Array-Processed Stacked Semiconductor Packages  
One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating...
US20080150103 Multi-Die Ic Package and Manufacturing Method  
A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of...
US20070249094 Method for fabricating multi-chip semiconductor package  
A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder...
US20100096741 Chip-Stacked Package Structure and Method for Manufacturing the Same  
A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a...
US20100047967 METHOD OF MANUFACTURING STACKED SEMICONDUCTOR PACKAGE USING IMPROVED TECHNIQUE OF FORMING THROUGH VIA  
A method of manufacturing a stacked semiconductor package using an improved technique of forming a through via in order to enable 3-dimensional vertical interconnection of stacked packages is...
US20080185703 INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES  
A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an...
US20070170571 Low profile semiconductor system having a partial-cavity substrate  
A system (100), which has an electrically insulating substrate (101) with a thickness, a first and a second surface. Electrically conductive paths (110) extend through the insulating body from the...
US20070023886 METHOD FOR PRODUCING A CHIP ARRANGEMENT, A CHIP ARRANGEMENT AND A MULTICHIP DEVICE  
The present invention relates to a method and apparatus for producing a chip arrangement. In one embodiment, the method includes providing a first chip having an electrically operable structure, of...
US20110159639 Method for Making a Stackable Package  
The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first...
US20110115098 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION AND METHOD FOR MANUFACTURING THEREOF  
A method for manufacturing an integrated circuit package system includes: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the...
US20100032820 Stacked Memory Module  
Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed...
US20080230903 SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME  
A semiconductor chip constitutes a semiconductor device in which a plurality of semiconductor chips are laminated. The semiconductor chip includes a plurality of terminals which are to be connected...
US20080174008 Structure of Memory Card and the Method of the Same  
The present invention provides a structure of memory card comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed...
US20140015130 MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS  
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package...
US20100173454 MICROELECTRONIC PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAMES CONFIGURED FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS  
Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment...
US20080273314 PCB having embedded IC and method for manufacturing the same  
A multi-layer PCB includes a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-hole formed in the insulating layers so as to...
US20080088031 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME  
A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming...
US20130260510 3-D Integrated Circuits and Methods of Forming Thereof  
In one embodiment, a method of forming a semiconductor device includes stacking a second wafer with a first wafer and forming a through via extending through the second wafer while the second wafer...
US20110147911 STACKABLE CIRCUIT STRUCTURES AND METHODS OF FABRICATION THEREOF  
Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its...
US20100317153 Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street  
A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed the die. The trench extends to...
US20100123232 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING AN INTERNAL STRUCTURE PROTRUSION AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing an internal structure substrate having an internal structure substrate cavity; mounting an internal structure...
US20100059885 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER  
An integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and...
US20080315406 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE  
An integrated circuit package system includes a base substrate having a base substrate cavity, attaching a junction integrated circuit package over the base substrate with a portion of the junction...
US20110049694 Semiconductor Wafer-To-Wafer Bonding For Dissimilar Semiconductor Dies And/Or Wafers  
A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects...
US20100096737 STACKABLE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES  
Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality...
US20090302449 PACKAGED PRODUCTS, INCLUDING STACKED PACKAGE MODULES, AND METHODS OF FORMING SAME  
An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical...
US20080173998 CHIP ARRANGEMENT AND METHOD FOR PRODUCING A CHIP ARRANGEMENT  
A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first...
US20080150133 Semiconductor Chip Assembly And Fabrication Method Therefor  
A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is realized. This is achieved by the assembly...
US20140061951 PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME  
A method for manufacturing a package on package structure includes the step of: providing a package body comprising a first package device and a connection substrate, the first package device...
US20120043669 STACKED SEMICONDUCTOR CHIP DEVICE WITH THERMAL MANAGEMENT CIRCUIT BOARD  
A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the...
US20100320603 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING THEREOF  
A method for manufacturing an integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and...
US20090166846 PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS  
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first...
US20090146282 Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads  
A semiconductor package has a first semiconductor die mounted on a substrate. A conductive via is formed through the substrate. A first RDL is formed on a first surface of the substrate in...
US20090111217 Method of manufacturing chip-on-chip semiconductor device  
Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device...
US20120326300 LOW PROFILE PACKAGE AND METHOD  
In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer...
US20100144093 Integrated Circuit Device and Method of Manufacturing Thereof  
A method of manufacturing an integrated circuit (IC) device is disclosed. A wafer including multiple dies is processed to form solder bumps at the bond pad locations. A conductive substrate is...
US20090115069 SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor chip package having a molding layer is provided. The semiconductor chip package includes a semiconductor chip, a plurality of external connection terminals, and the molding layer....
US20060108677 Multi-chip package and method of fabricating the same  
A lower chip is fixed to a surface of an interposer by flip-chip bonding with an under fill acting as an adhesive applied to the surface. A lifted pad having a height of approximately 10 μm is ...
US20050046003 Stacked-chip semiconductor package and fabrication method thereof  
A stacked-chip semiconductor package and a fabrication method thereof are provided in which a thermal blocking member is applied over an opening formed through a chip carrier, with a first chip...
US20130113115 SYSTEM IN PACKAGE PROCESS FLOW  
A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the...
US20110045636 LIGHTWEIGHT AND COMPACT THROUGH-SILICON VIA STACK PACKAGE WITH EXCELLENT ELECTRICAL CONNECTIONS AND METHOD FOR MANUFACTURING THE SAME  
A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an...
US20090325343 BONDED SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME  
A method of forming a bonded semiconductor structure circuit includes providing a support substrate which carries a first semiconductor circuit and providing a first interconnect region carried by...
US20090079091 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER  
An integrated circuit packaging system comprising: fabricating an interposer array having an access opening; fabricating a base package substrate sheet; attaching a first integrated circuit die...
US20080029879 Structure and method of making lidded chips  
Lidded chip packages are provided in which an optoelectronic device chip has microelectronic circuits exposed at a surface of the chip with a lid mounted to overlie the optoelectronic device and...
US20120241980 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COLLAPSED MULTI-INTEGRATION PACKAGE AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having...
US20110227209 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit package system includes: forming a base package including: fabricating a base package substrate having a component side and a system side, coupling...
US20110147901 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF  
A method of manufacture of an integrated circuit packaging system includes forming a lead frame including providing a tie bar plate, forming conductive columns on the tie bar plate, forming a...
US20110084402 PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES  
Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly...
US20100022052 Method for manufacturing package on package with cavity  
A manufacturing method of a package on package with a cavity. The method can include forming a first upper substrate cavity in one side of an upper substrate; mounting an upper semiconductor chip...
US20090283889 INTEGRATED CIRCUIT PACKAGE SYSTEM  
An integrated circuit package system includes: providing a heat spreader; attaching an upper substrate to the heat spreader, the upper substrate having an upper through-opening provided therein;...