Matches 1 - 50 out of 56 1 2 >


Match Document Document Title
US20110164711 DECODER AND METHOD FOR ADAPTIVELY GENERATING A CLOCK WINDOW  
A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a...
US20120014489 METHOD AND SYSTEM FOR MAINTAINING WIRELESS LINKS IN A COMMUNICATION NETWORK  
A method of operating a communication system comprises sending a frame by an access node to a wireless device where the frame comprises a packet. A counter is initialized and a timer for each...
US20150071393 LOW POWER DIGITAL FRACTIONAL DIVIDER WITH GLITCHLESS OUTPUT  
A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to...
US20090086869 METHOD AND SYSTEM OF RECEIVING TAG SIGNAL FROM RFID READER  
Disclosed are a method and system for receiving a tag signal in a Radio Frequency Identification (RFID) reader. The method includes generating an edge signal using a tag signal received from an...
US20120082280 SAMPLER CIRCUIT  
A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous...
US20100316175 Packet detection, synchronization, and frequency offset estimation  
Techniques are disclosed for detecting a packet. One technique includes sampling a received signal to produce a sequence of samples wherein the sequence of samples includes a plurality of...
US20090154626 CONTINUOUS RECEIVER CLOCK ALIGNMENT AND EQUALIZATION OPTIMIZATION  
The available bandwidth of an Input/Output (I/O) communications link is increased by removing the need for retraining events on a communications link. This results in removing a potentially severe...
US20130003905 TRANSITION DETECTOR  
An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first...
US20080101517 Smart Antenna Interface Using Only Digital I/O Supporting Both Mode A and Mode B Antenna Operation as Per CEA 909 Standard Using a Single Digital Counter  
This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B operation. This invention implements...
US20140294131 CLOCK DETERMINATION FOR A SENSOR  
A method for determining a clock for a sensor signal which has a synchronization signal, which method involves a control unit measuring the period between a first edge and a second edge of the...
US20070019770 Microprocessor programmable clock calibration system and method  
A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares...
US20090310978 COMPLEMENTARY OPTICAL WIRING SYSTEM  
A complementary optical wiring system has a transmitting circuit configured to combine a delayed signal obtained by delaying a digital electric input signal by a time shorter than a minimum pulse...
US20100002821 CLOCK DETERMINATION FOR A SENSOR  
A method for determining a clock for a sensor signal which has a synchronization signal, which method involves a control unit measuring the period between a first edge and a second edge of the...
US20090196388 SIGNAL TRANSMISSION SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by...
US20090122935 False frequency lock detector  
A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge...
US20090290670 METHOD OF ACQUIRING INITIAL SYNCHRONIZATION IN IMPULSE WIRELESS COMMUNICATION AND RECEIVER  
A receiver in an impulse wireless communication. The receiver (300) includes a pulse-pair correlator (304) that receives a signal (316) and divides it into two signals for paths. One of the...
US20070076831 Dual-reference delay-locked loop (DLL)  
Embodiments of the present invention are directed to a dual-reference delay-locked loop that includes a first delay element that delays a clock signal. The rising phase and the falling phase of...
US20090116593 CIRCUIT FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN HIGH SPEED SERIAL LINKS  
Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the...
US20070127612 Apparatus and method for retiming data using phase-interpolated clock signal  
A data recovering apparatus and method using an interpolated clock signal are provided. The data recovering apparatus comprises a first phase alignment unit extracting from multi-phase clock...
US20090122936 METHOD AND CIRCUIT FOR DYNAMICALLY CHANGING THE FREQUENCY OF CLOCK SIGNALS  
A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock...
US20060274873 Rapid data point selection for generating eye diagrams  
A method and an apparatus for constructing an eye diagram. Occurrences of a first value in a signal are counted during a time interval. A second value is selected as a function of this occurrence...
US20050243957 Clock extraction circuit for use in a linearly expandable broadcast router  
A method for extracting selected time information from a stream of serialized AES digital audio data. A first transition of a first preamble of said stream of serialized AES digital audio data is...
US20080198957 APPARATUS, METHOD, AND PROGRAM FOR VERIFYING LOGIC CIRCUIT OPERATING WITH MULTIPLE CLOCK SIGNALS  
A verification apparatus that can verify a circuit in a shorter time while taking possible metastability into consideration. A clock domain crossing (CDC) detector finds CDC paths between circuit...
US20090092212 CLOCK EMBEDDED DIFFERENTIAL DATA RECEIVING SYSTEM FOR TERNARY LINES DIFFERENTIAL SIGNALING  
A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors...
US20060222132 Receive timing manager  
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data...
US20140254732 TRANSCODING METHOD FOR MULTI-WIRE SIGNALING THAT EMBEDS CLOCK INFORMATION IN TRANSITION OF SIGNAL STATE  
A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m...
US20100172400 ADAPTIVE EQUALIZATION APPARATUS WITH EQUALIZATION PARAMETER SETTING ADPATIVELY ADJUSTED ACCORDING TO EDGES OF EQUALIZER OUTPUT MONITORED IN REAL-TIME MANNER AND RELATED METHOD THEREOF  
An adaptive equalization apparatus is provided. The adaptive equalization apparatus includes an equalizer, a monitor circuit, and a control circuit. The equalizer receives a first signal, and...
US20090225918 DETECTION OF FREQUENCY CORRECTION BURSTS AND THE LIKE  
In one embodiment, a frequency correction (FC) burst is detected in a complex signal received by a mobile station of a GSM/EDGE wireless communications network by applying the complex signal to...
US20070064848 Clock recovery  
A method and apparatus of recovering a clock signal from an input data signal consistent with certain embodiments, where the clock signal has a clock cycle equal to one data bit period, involves...
US20080310571 Pulsed Serial Link Transmitting Data and Timing Information on a Single Line  
A method of encoding data and timing information on a single line comprising: asserting a first edge on the single line to encode said timing information; asserting a second edge on the single...
US20080170650 Fast Time-Scale Modification of Digital Signals Using a Directed Search Technique  
The time-scale of a digital signal is efficiently modified. A system suitable for embedded or stand-alone processing includes a module that can transform the time-scale of the signal according to...
US20090116598 Semiconductor memory device having data clock training circuit  
A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a...
US20060153326 Serial data communication apparatus and methods of using a single line  
Serial data communication methods and apparatus using a single line are provided. The data communication methods may include: setting a rising edge of a serial pulse signal so that a cycle of the...
US20090261662 METHOD FOR SUPPLYING ELECTRICAL ENERGY FROM A FIRST ELECTRONIC CIRCUIT TO A SECOND ELECTRONIC SIRCUIT VIA AT LEAST ONE WIRE LINE  
A method of supplying electrical energy from a first electronic circuit (10) to a second electronic circuit (20) connected via a communication interface (30), which interface (30) comprises at...
US20150146831 SENSOR, CONTROL UNIT AND METHOD TO COMMUNICATE BETWEEN SENSORS AND CONTROL UNITS  
A sensor may include a clock generator configured to generate a clock. A receiver may be configured to receive signals from a control unit, and a transmitter they be configured to send signals to...
US20090310727 METHOD AND DEVICE FOR THE GENERATION OF OUT-OF-PHASE BINARY SIGNALS, AND USE OF THE SAME  
A method for the generation of binary signals (So1, So2, So3) which are out-of-phase with a control phase angle (?) which is continuously variable in relation to at least one synchronisation...
US20070081618 Apparatus and method for recovering clock and data  
An apparatus for recovering a clock and data includes a transition detecting circuit and a clock recovery circuit. The transition detecting circuit detects a transition of an input data signal to...
US20110008055 Combined Burst Mode Level and Clock Recovery  
An apparatus comprising an optical receiver configured to receive an optical signal, and a combined level and clock recovery circuit coupled to the optical receiver and configured to update a...
US20080267330 FEEDBACK OF REINTERLEAVED CORRECTLY DECODED DATA BLOCK TO DECODER FOR USE IN ADDITIONAL CHANNEL DECODING OPERATIONS OF CHANNEL CODED WORD CONTAINING DATA BLOCK  
The feedback of reinterleaved correctly decoded data blocks to a decoder is provided for use in channel decoding operations of channel coded word containing data block. Once a properly decoded...
US20080117952 SELF-SUPPORTING SIMPLEX PACKETS  
Existing message fields and/or message parameters are configured to facilitate the packet and message synchronization and decoding tasks that conventionally rely upon a known bit sequence in each...
US20150030112 THREE PHASE CLOCK RECOVERY DELAY CALIBRATION  
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity...
US20080107220 METHODS AND APPARATUS FOR SIGNAL AND TIMING DETECTION IN WIRELESS COMMUNICATION SYSTEMS  
In accordance with a detection method in a wireless communication system, an initial hypothesis for a starting position of a desired signal within a received wireless communication signal may be...
US20120121051 RECEIVE TIMING MANAGER  
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data...
US20080049882 Receiving Device for Receiving Time-Multiplexed Signals, Transmitting System, and Method for Time Synchronization of Time-Multiplexed Signals  
In a receiving device for receiving a time-multiplexed signal on one carrier frequency and for reading out a content datum of a further time-multiplexed signal on a further carrier frequency, a...
US20090135975 APPARATUS AND METHOD FOR RECOVERING DATA  
An apparatus for recovering data and a method thereof are provided. The apparatus includes a reference clock generator which generates a reference clock, and a data recovering unit which detects...
US20100128831 CIRCUIT FOR DETECTING CLOCK AND APPARATUS FOR PROVIDING CLOCK  
A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last...
US20100104057 Clock and Data Recovery with a Data Aligner  
In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered...
US20160080140 A NETWORK RECEIVER FOR A NETWORK USING DISTRIBUTED CLOCK SYNCHRONIZATION AND A METHOD OF ADJUSTING A FREQUENCY OF AN INTERNAL CLOCK OF THE NETWORK RECEIVER  
A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver...
US20150358149 WIRELESS DEVICE AND METHOD FOR CONTROLLING WIRELESS DEVICE  
A wireless device including an oscillator circuit, a detector circuit, and a controller circuit. The oscillator circuit generate a clock signal. The detector circuit detect respective phase...
US20150270946 SIMULTANEOUS TRANSMISSION OF CLOCK AND BIDIRECTIONAL DATA OVER A COMMUNICATION CHANNEL  
Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a...

Matches 1 - 50 out of 56 1 2 >