Sign up


Match Document Document Title
US20130215686 REFERENCE GENERATOR WITH PROGRAMMABLE M AND B PARAMETERS AND METHODS OF USE  
A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a...
US20120087187 Method for Programming a Floating Gate  
The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an...
US20110026324 Method for Programming a Floating Gate  
The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an...
US20080023344 Collectable display panel and data storage device  
A collectable display panel and data storage device is described. The invention involves at least one display panel that is formed for housing and displaying at least one collectable object, such...
US20130235658 METHOD FOR PROGRAMMING A FLOATING GATE  
The present invention provides circuits, systems, and methods for programming a floating gate. As described herein, a floating gate tunneling device is used with an analog comparison device in a...
US20130301343 THRESHOLD VOLTAGE MEASUREMENT DEVICE  
A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating...
US20120020176 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS  
Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a...
US20110158031 SIGNAL CALIBRATION METHODS AND APPARATUSES  
In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed...
US20130128666 Scrub Techniques for Use with Dynamic Read  
The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured...
US20130193944 VOLTAGE GENERATOR  
According to one embodiment, a voltage generator includes a step-up circuit and a limiter circuit. The step-up circuit outputs a first voltage to a first node. The limiter circuit includes first...
US20080070162 Information storage elements and methods of manufacture thereof  
An information storage element has a carbon storage material including hexagonally bonded carbon and tetrahedrally bonded carbon. The information is formed by a changeable ratio of hexagonally...
US20080285375 SEMICONDUCTOR DEVICE, MODULE INCLUDING THE SEMICONDUCTOR DEVICE, AND SYSTEM INCLUDING THE MODULE  
A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a...
US20080084747 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE  
A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile...
US20120087183 METHODS OF OPERATING PRAMS USING INITIAL PROGRAMMED RESISTANCES AND PRAMS USING THE SAME  
A method of operating a PRAM device can be provided by reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial...
US20100002515 Programming And Selectively Erasing Non-Volatile Storage  
A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements...
US20100091539 SOLID STATE DEVICE PRODUCTS, INTERMEDIATE SOLID STATE DEVICES, AND METHODS OF MANUFACTURING AND TESTING THE SAME  
Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test...
US20140003155 SPLIT GATE PROGRAMMING  
A method for programming a split gate memory cell includes performing a first programming of the split gate memory cell in a first programming cycle of the split gate memory cell; and, subsequent...
US20130294179 CIRCUITS AND METHODS FOR CALIBRATING OFFSET IN AN AMPLIFIER  
In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of...
US20110141824 LEAKAGE COMPENSATED REFERENCE VOLTAGE GENERATION SYSTEM  
An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to...
US20110261608 Self-Repairing Memristor and Method  
A self-repairing memristor (300) and methods of operating a memristor (10), (310) and repairing a memristor (10), (310) employ thermal annealing (110). The thermal annealing (110) removes a short...
US20140029327 BIPOLAR RESISTIVE SWITCH HEAT MITIGATION  
A heat mitigated bipolar resistive switch includes a BRS matrix sandwiched between first and second electrodes and a heat mitigator. The BRS matrix is to support bipolar switching of a conduction...
US20140003135 SRAM BITCELL IMPLEMENTED IN DOUBLE GATE TECHNOLOGY  
An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first...
US20120008431 INTEGRATED CIRCUIT USING METHOD FOR SETTING LEVEL OF REFERENCE VOLTAGE  
An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an...
US20130163340 NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE  
A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The...
US20080273410 Tungsten digitlines  
Methods, devices, and systems for using and forming tungsten digitlines have been described. The tungsten digitlines formed according to embodiments of the present disclosure can be formed with a...
US20110199837 High Voltage Word Line Driver  
A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the...
US20060050580 Method for generating identification code of semiconductor device, method for identifying semiconductor device and semiconductor device  
A semiconductor device including memory cells such as flip-flops, RAMs or SRAMs is powered on, and first logic signals of Hi or Lo output from the respective memory cells are obtained. A...
US20110026309 SELF-TIMED WRITE BOOST FOR SRAM CELL WITH SELF MODE CONTROL  
A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at...
US20140043927 METHOD FOR OPTIMIZING REFRESH RATE FOR DRAM  
A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating...
US20120087196 GATE OXIDE BREAKDOWN-WITHSTANDING POWER SWITCH STRUCTURE  
The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively...
US20090080245 OFFSET NON-VOLATILE STORAGE  
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce...
US20060092751 Peripheral management  
A peripheral management system includes a listing of a plurality of peripheral types and at least one driver associated with selected ones of the plurality of peripheral types.
US20100091596 SOLID STATE DRIVE SYSTEMS AND METHODS OF REDUCING TEST TIMES OF THE SAME  
Example embodiments of the inventive concept are directed to solid state device systems and methods of reducing test times of the same.
US20090201734 Verified purge for flash storage device  
A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller...
US20130107655 Lookahead Scheme for Prioritized Reads  
A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data...
US20120087199 WAKE-UP CONTROL CIRCUIT FOR POWER-GATED IC  
Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a...
US20110075470 EMBEDDED SRAM STRUCTURE AND CHIP  
An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least...
US20130223175 VOLTAGE GENERATORS ADAPTIVE TO LOW EXTERNAL POWER SUPPLY VOLTAGE  
Voltage generators may generate a level of a high target voltage with respect to a low external power supply voltage. A reference voltage generator includes a clamp regulator which is driven by a...
US20100002513 Selective Erase Operation For Non-Volatile Storage  
A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control...
US20090316462 MAGNETIC TRACKS WITH DOMAIN WALL STORAGE ANCHORS  
Magnetic shift registers in which data writing and reading is accomplished by moving the magnetic domain walls by electric current. Various embodiments of domain wall nodes or anchors that...
US20130028014 REFERENCE VOLTAGE GENERATORS AND SENSING CIRCUITS  
Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which...
US20090046513 Enhanced erase for flash storage device  
A flash storage device includes flash storage units that are erased in response to a condition or command while allowing the flash storage device to be used subsequent to the erase. A flash...
US20120127788 MRAM Cells and Circuit for Programming the Same  
A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured...
US20110242919 Precharge Voltage Supplying Circuit  
A precharge voltage supplying circuit comprises a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is...
US20100002514 Correcting For Over Programming Non-Volatile Storage  
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
US20090296475 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE  
When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process...
US20110051532 REFERENCE LEVEL GENERATION WITH OFFSET COMPENSATION FOR SENSE AMPLIFIER  
An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset...
US20140050029 SPLIT-GATE MEMORY CELLS HAVING SELECT-GATE SIDEWALL METAL SILICIDE REGIONS AND RELATED MANUFACTURING METHODS  
Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose...
US20100321985 Boosted gate voltage programming for spin-torque MRAM array  
A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device...
US20100328987 E-FUSE APPARATUS FOR CONTROLLING REFERENCE VOLTAGE REQUIRED FOR PROGRAMMING/READING E-FUSE MACRO IN AN INTEGRATED CIRCUIT VIA SWITCH DEVICE IN THE SAME INTEGRATED CIRCUIT  
An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The...