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US20120087187 |
Method for Programming a Floating Gate
The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an...
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US20110026324 |
Method for Programming a Floating Gate
The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an...
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US20080023344 |
Collectable display panel and data storage device
A collectable display panel and data storage device is described. The invention involves at least one display panel that is formed for housing and displaying at least one collectable object, such...
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US20120020176 |
GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS
Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a...
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US20110158031 |
SIGNAL CALIBRATION METHODS AND APPARATUSES
In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed...
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US20080070162 |
Information storage elements and methods of manufacture thereof
An information storage element has a carbon storage material including hexagonally bonded carbon and tetrahedrally bonded carbon. The information is formed by a changeable ratio of hexagonally...
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US20080285375 |
SEMICONDUCTOR DEVICE, MODULE INCLUDING THE SEMICONDUCTOR DEVICE, AND SYSTEM INCLUDING THE MODULE
A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a...
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US20080084747 |
REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE
A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile...
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US20120087183 |
METHODS OF OPERATING PRAMS USING INITIAL PROGRAMMED RESISTANCES AND PRAMS USING THE SAME
A method of operating a PRAM device can be provided by reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial...
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US20100002515 |
Programming And Selectively Erasing Non-Volatile Storage
A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements...
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US20100091539 |
SOLID STATE DEVICE PRODUCTS, INTERMEDIATE SOLID STATE DEVICES, AND METHODS OF MANUFACTURING AND TESTING THE SAME
Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test...
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US20110141824 |
LEAKAGE COMPENSATED REFERENCE VOLTAGE GENERATION SYSTEM
An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to...
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US20110261608 |
Self-Repairing Memristor and Method
A self-repairing memristor (300) and methods of operating a memristor (10), (310) and repairing a memristor (10), (310) employ thermal annealing (110). The thermal annealing (110) removes a short...
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US20120008431 |
INTEGRATED CIRCUIT USING METHOD FOR SETTING LEVEL OF REFERENCE VOLTAGE
An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an...
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US20080273410 |
Tungsten digitlines
Methods, devices, and systems for using and forming tungsten digitlines have been described. The tungsten digitlines formed according to embodiments of the present disclosure can be formed with a...
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US20110199837 |
High Voltage Word Line Driver
A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the...
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US20060050580 |
Method for generating identification code of semiconductor device, method for identifying semiconductor device and semiconductor device
A semiconductor device including memory cells such as flip-flops, RAMs or SRAMs is powered on, and first logic signals of Hi or Lo output from the respective memory cells are obtained. A...
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US20110026309 |
SELF-TIMED WRITE BOOST FOR SRAM CELL WITH SELF MODE CONTROL
A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at...
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US20120087196 |
GATE OXIDE BREAKDOWN-WITHSTANDING POWER SWITCH STRUCTURE
The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively...
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US20090080245 |
OFFSET NON-VOLATILE STORAGE
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce...
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US20060092751 |
Peripheral management
A peripheral management system includes a listing of a plurality of peripheral types and at least one driver associated with selected ones of the plurality of peripheral types.
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US20100091596 |
SOLID STATE DRIVE SYSTEMS AND METHODS OF REDUCING TEST TIMES OF THE SAME
Example embodiments of the inventive concept are directed to solid state device systems and methods of reducing test times of the same.
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US20090201734 |
Verified purge for flash storage device
A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller...
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US20130107655 |
Lookahead Scheme for Prioritized Reads
A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data...
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US20120087199 |
WAKE-UP CONTROL CIRCUIT FOR POWER-GATED IC
Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a...
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US20110075470 |
EMBEDDED SRAM STRUCTURE AND CHIP
An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least...
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US20100002513 |
Selective Erase Operation For Non-Volatile Storage
A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control...
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US20090316462 |
MAGNETIC TRACKS WITH DOMAIN WALL STORAGE ANCHORS
Magnetic shift registers in which data writing and reading is accomplished by moving the magnetic domain walls by electric current. Various embodiments of domain wall nodes or anchors that...
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US20130028014 |
REFERENCE VOLTAGE GENERATORS AND SENSING CIRCUITS
Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which...
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US20090046513 |
Enhanced erase for flash storage device
A flash storage device includes flash storage units that are erased in response to a condition or command while allowing the flash storage device to be used subsequent to the erase. A flash...
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US20120127788 |
MRAM Cells and Circuit for Programming the Same
A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured...
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US20110242919 |
Precharge Voltage Supplying Circuit
A precharge voltage supplying circuit comprises a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is...
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US20100002514 |
Correcting For Over Programming Non-Volatile Storage
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
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US20090296475 |
VERIFICATION PROCESS FOR NON-VOLATILE STORAGE
When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process...
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US20110051532 |
REFERENCE LEVEL GENERATION WITH OFFSET COMPENSATION FOR SENSE AMPLIFIER
An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset...
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US20100321985 |
Boosted gate voltage programming for spin-torque MRAM array
A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device...
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US20100328987 |
E-FUSE APPARATUS FOR CONTROLLING REFERENCE VOLTAGE REQUIRED FOR PROGRAMMING/READING E-FUSE MACRO IN AN INTEGRATED CIRCUIT VIA SWITCH DEVICE IN THE SAME INTEGRATED CIRCUIT
An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The...
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US20110292733 |
ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF
A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed...
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US20130107631 |
Method Of Programming A Split Gate Non-volatile Floating Gate Memory Cell Having A Separate Erase Gate
A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of...
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US20090003093 |
FUSE READING CIRCUIT
Correction data is written in fuse circuits of q bits. A reading circuit sequentially reads information of the fuse circuits through a selector and writes the information in a storage circuit....
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US20110222337 |
FLOATING-BODY/GATE DRAM CELL
Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated...
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US20050152192 |
Reducing occupancy of digital storage devices
A digital data storage device physically stores blocks of identical data only once on its storage medium wherein a second or even further identical blocks are stored only as reference referring to...
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US20110235454 |
High-voltage selecting circuit which can generate an output voltage without a voltage drop
A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage...
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US20120106255 |
VOLTAGE GENERATION CIRCUIT WHICH IS CAPABLE OF REDUCING CIRCUIT AREA
According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first...
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US20080289565 |
Rescue whistle
A rescue whistle, end surfaces of two ends of which are respectively concaved with a holding space, a circuit board main body at one end of a flash drive storage unit is positioned within one of...
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US20120106237 |
BOOST CIRCUIT FOR GENERATING AN ADJUSTABLE BOOST VOLTAGE
A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also...
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US20110249516 |
INTERNAL VOLTAGE GENERATION DEVICE
An internal voltage generation device is disclosed which includes an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal...
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US20110069563 |
VOLTAGE SHIFTER FOR HIGH VOLTAGE OPERATIONS
A voltage shifter has a supply line receiving a supply voltage that varies between a first operating value in a first operating condition and a second high operating value, in a second operating...
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US20120327700 |
LOW VOLTAGE METAL GATE ANTIFUSE WITH DEPLETION MODE MOSFET
An antifuse according to an embodiment of the invention herein can include a depletion mode metal oxide semiconductor field effect transistor (“MOSFET”) having a conduction channel and a metal gat...
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US20110280094 |
Boost Cell Supply Write Assist
A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said...
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