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US20150179240 SHARING RESOURCES IN MULTI-DICE STACKS  
Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the unique identifier are provided....
US20150036417 SRAM READ BUFFER WITH REDUCED SENSING DELAY AND IMPROVED SENSING MARGIN  
A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is...
US20050063256 Data storage in optical discs  
A device for preventing and controlling copying of data from an optical storage disc utilizing physical modifications in or on a storage capable optical disc. Also described is a method for...
US20110280064 COMPOSITE RESISTANCE VARIABLE ELEMENT AND METHOD FOR MANUFACTURING THE SAME  
A composite resistance variable element includes a first resistance variable element in which a resistance value varies corresponding to a direction of inner magnetization, and a second resistance...
US20150131379 BAD BLOCK COMPENSATION FOR SOLID STATE STORAGE DEVICES  
Technologies and implementations for reusing bad blocks in a solid state drive are generally disclosed.
US20110080770 METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT AND NONVOLATILE STORAGE DEVICE  
Applying a writing voltage pulse having a first polarity to a metal oxide layer (3) to change a resistance state of the metal oxide layer (3) from high to low so as to render the resistance state...
US20090175089 Retention in NVM with top or bottom injection  
Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM,...
US20130003446 Method for Extending Word-Line Pulses  
An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of...
US20110085399 Method for Extending Word-Line Pulses  
An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of...
US20090091997 SEMICONDUCTOR MEMORY DEVICE SUITABLE FOR MOUNTING ON PORTABLE TERMINAL  
A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives...
US20060152991 Non-volatile memory storage of fuse information  
A fuse-free circuit may include a NAND flash memory cell, and a switch to turn on or off in response to data stored in the NAND flash memory cell. The fuse-free circuit may be embodied in a...
US20110286281 REFERENCE CURRENT GENERATOR USED FOR PROGRAMMING AND ERASING OF NON-VOLATILE MEMORY  
A reference current generator used for programming and erasing of the non-volatile memory. Wherein, a self-biasing reference generator is used to generate a first reference voltage of a negative...
US20140192600 EEPROM CELL AND EEPROM DEVICE  
An EEPROM cell is provided which includes a control gate; a tunneling plate; a floating plate configured to form a capacitor area with the control plate and the tunneling plate; an inverter...
US20120044744 PROGRAMMABLY REVERSIBLE RESISTIVE DEVICE CELLS USING POLYSILICON DIODES  
Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices such as PCRAM, RRAM, CBRAM, or other memory cells. The reversible...
US20130182494 SKEWED SRAM CELL  
A memory cell including a cross-coupled latch with corresponding storage nodes, and further including first and second write pass gate transistors and first and second read pass gate transistors....
US20090207673 SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI TEST  
A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches...
US20110235445 METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF REGISTER FILES  
A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register...
US20120075919 Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability  
Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and...
US20120236672 HIGH VOLTAGE GENERATING CIRCUIT AND METHOD OF OPERATING THE SAME  
A high voltage generating circuit includes first and second high voltage pump circuits and an oscillator. The oscillator is configured to output a first clock signal driving the first high voltage...
US20070109833 Daisy chain cascading devices  
A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs...
US20120039143 SENSE AMPLIFIER WITH ADJUSTABLE BACK BIAS  
A circuit having a sensing circuit and at least one of a first node and a second node is described. The sensing circuit includes a pair of a first type transistors and a pair of a second type...
US20100080047 SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS  
Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin...
US20150255174 MEMORY TESTING METHOD AND APPARATUS  
A method and an apparatus for testing a memory are provided, where the memory includes a plurality of sectors each of which includes a plurality of bytes, and the testing is performed to the...
US20080117694 Semiconductor device and semiconductor chips  
High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b...
US20130088927 SYSTEM AND METHOD FOR GENERATING A CLOCK  
A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking...
US20100085824 Semiconductor device having delay control circuit  
A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which...
US20140355334 HANDSHAKING SENSE AMPLIFIER  
Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also...
US20080055957 Three-Dimensional Memory Module (3D-MM) Excelling Contemporary Micro-Drive (CMD)  
The present invention discloses a three-dimensional memory module (3D-MM), which excels contemporary micro-drive (CMD) in both physical size and storage capacity. Three-dimensional memory...
US20130235687 Asymmetric Sense Amplifier Design  
A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first...
US20120213010 Asymmetric Sense Amplifier Design  
A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first...
US20070189058 Molecular system and method for reversibly switching the same between four states  
A molecular system that is reversibly switchable between four states includes two or more ends. At least three rotors and at least two stators are located between the ends. Each of the rotors is...
US20090175062 FEEDBACK STRUCTURE FOR AN SRAM CELL  
Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the...
US20090052230 INTEGRATED CIRCUIT INCLUDING SILICIDE REGION TO INHIBIT PARASITIC CURRENTS  
An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first...
US20140092674 Circuits and Methods of a Self-Timed High Speed SRAM  
Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near...
US20120257463 DRIVER CIRCUIT  
A driver circuit includes pull-up and pull-down drivers driven by separate pre-drivers operating between different voltage rails. Data signals driving the pull-up driver and the pull-down driver...
US20150248922 DIVIDING A STORAGE PROCEDURE  
Apparatuses, systems, methods, and computer program products are disclosed for storage operations for a non-volatile medium. A control module may be configured to divide a storage procedure into...
US20140185353 MEMORY  
A memory in accordance with an embodiment of the present invention may include a first page buffer, a second page buffer arranged adjacent to the first page buffer in a first direction, a global...
US20100322026 MECHANISM FOR MEASURING READ CURRENT VARIABILITY OF SRAM CELLS  
A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The...
US20090180313 Chalcogenide anti-fuse  
An ovonic threshold switch may be used to form an anti-fuse. As manufactured, the fuse may be in its amorphous state, as is conventional for ovonic threshold switches. However, when exposed to a...
US20110069562 LOW CONSUMPTION VOLTAGE REGULATOR FOR A HIGH VOLTAGE CHARGE PUMP, VOLTAGE REGULATION METHOD, AND MEMORY DEVICE PROVIDED WITH THE VOLTAGE REGULATOR  
A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch...
US20080089126 CIRCUITRY FOR RELIABILITY TESTING AS A FUNCTION OF SLEW  
A reliability test chain includes: a stress chain; and transition time control circuits coupled to tap points along the stress chain such that transition times of a signal on the stress chain are...
US20090190432 DRAM with Page Access  
A DRAM chip with a data I/O-interface of an access width equal to a page size.
US20130176806 POWER-UP SIGNAL GENERATION CIRCUIT  
A power-up signal generation circuit includes a first driving section configured to generate a pre-power-up signal by driving a first node to a first pull-up drivability or driving the first node...
US20130070519 READ ARCHITECTURE FOR MRAM  
A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense...
US20080316827 NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS  
A non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between...
US20140355353 CURRENT SENSING AMPLIFIER AND SENSING METHOD THEREOF  
A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference...
US20080219068 ZQ CALIBRATION CONTROLLER AND METHOD FOR ZQ CALIBRATION  
A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a...
US20090201732 System and method for purging a flash storage device  
A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and...
US20130044535 REFERENCE CELL CIRCUIT AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE INCLUDING THE SAME  
Included are reference cells each including a variable resistance element which reversibly changes between a predetermined low resistance state LR and a predetermined high resistance state HR...
US20150071012 SUPPLY INDEPENDENT DELAYER  
Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control...