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US20100073991 STORAGE APPARATUS  
According to one embodiment, a storage apparatus includes: a first inverter; a second inverter; a first storage element having a first state and a second state; and a second storage element having...
US20150228322 NMOS-OFFSET CANCELING CURRENT-LATCHED SENSE AMPLIFIER  
A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit...
US20070243620 Analysis and Screening of Solid Forms Using the Atomic Pair Distribution Function  
A method that comprises providing a PDF trace of a first sample of a substance, providing a PDF trace of a second sample of the substance, and comparing the PDF traces to determine whether the...
US20140071750 ADAPTIVE WORD-LINE BOOST DRIVER  
A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the...
US20060181912 Low-power solid state storage controller for cell phones and other portable appliances  
A storage controller comprising a first interface to exchange data with an appliance, such as a cell phone; a second interface to exchange data with a host system and receive power from the host...
US20120063202 3T DRAM CELL WITH ADDED CAPACITANCE ON STORAGE NODE  
A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a...
US20110222355 Control voltage generation circuit and nonvolatile storage device having the same  
Disclosed herein is a control voltage generation circuit including: a reference voltage generation circuit adapted to generate a reference voltage; and a voltage conversion circuit adapted to...
US20130329493 Natural Threshold Voltage Distribution Compaction In Non-Volatile Memory  
In a non-volatile memory system, a programming operation is performed in which faster-programming storage elements are distinguished from slower-programming storage elements. In one approach, the...
US20060187729 Source synchronous communication channel interface receive logic  
A network device for determining an optimal sampling phase for source synchronous data received on a data communications channel. The network device includes a transmitter clock domain for...
US20130258750 DUAL-CELL MTJ STRUCTURE WITH INDIVIDUAL ACCESS AND LOGICAL COMBINATION ABILITY  
A dual-cell spin-transfer torque random-access memory including a first magnetic tunneling junction and a second magnetic tunneling junction. An access circuit is coupled to the first and second...
US20150262692 READ MARGIN MEASUREMENT IN A READ-ONLY MEMORY  
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate...
US20150255164 READ MARGIN MEASUREMENT IN A READ-ONLY MEMORY  
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate...
US20140140141 READ MARGIN MEASUREMENT IN A READ-ONLY MEMORY  
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate...
US20110122694 LIMITATION OF THE ACCESS TO A RESOURCE OF AN ELECTRONIC CIRCUIT  
A method and a circuit for controlling the access to at least one resource of an electronic circuit, in which a test of the value of a counter over at least one bit conditions the access to the...
US20130003443 8T SRAM CELL WITH HIGHER VOLTAGE ON THE READ WL  
The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the...
US20150062995 RADIATION-HARDENED STORAGE UNIT  
A radiation-hardened storage unit, including a basic storage unit, a redundant storage unit, and a two-way feedback unit. The basic storage unit includes a first PMOS transistor, a second PMOS...
US20130215673 MAGNETORESISTIVE LOGIC CELL AND METHOD OF USE  
A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable...
US20120213015 SENSE AMPLIFIER  
A sense amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS...
US20100074008 SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES  
Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting...
US20120014171 SCHMITT TRIGGER-BASED FINFET SRAM CELL  
The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new...
US20130343129 EXTENDED SELECT GATE LIFETIME  
A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a...
US20050018506 Sense amp equilibration device  
A dynamic random access memory sense amp equilibration and biasing circuit with reduced transistor count allowing an interstitial layout, thus substantially reducing circuit area requirements.
US20110267888 Controlling Select Gate Voltage During Erase To Improve Endurance In Non-Volatile Memory  
A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase...
US20090180337 Data bus power-reduced semiconductor storage apparatus  
In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced,...
US20140293709 SINGLE-LAYER GATE EEPROM CELL, CELL ARRAY INCLUDING THE SAME, AND METHOD OF OPERATING THE CELL ARRAY  
A cell array portion of a single-layer gate EEPROM device includes a plurality of unit cells formed over a substrate to share a first well region in the substrate. Each of the plurality of unit...
US20130148432 SENSE AMPLIFIER WITH OFFSET CURRENT INJECTION  
A sense amplifier includes a sense input node, a current mirror circuit to mirror the current on the sense input node, and a result output node. A current source supplies an offset current. The...
US20100008170 Semiconductor tester and testing method of semiconductor memory  
The disclosure concerns a semiconductor tester for testing a memory under test. The semiconductor tester comprises a pattern generator generating address information on the pages and generating a...
US20130148452 VOLTAGE SHIFTING SENSE AMPLIFIER FOR SRAM VMIN IMPROVEMENT  
A sense amplifier for a SRAM device includes a PMOS differential pair and an NMOS differential pair to support operation with bit line precharge voltage as low as a few hundred millivolts without...
US20120039125 Nonvolatile Memory with Correlated Multiple Pass Programming  
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are...
US20110019471 Nonvolatile Memory with Correlated Multiple Pass Programming  
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are...
US20130329513 DELAY-LOCKED LOOP HAVING A LOOP BANDWIDTH DEPENDENCY ON PHASE ERROR  
Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a...
US20110170366 TEMPERATURE DETECTOR IN AN INTEGRATED CIRCUIT  
A method for determining a temperature in a circuit comprises receiving a periodic signal. A frequency of the periodic signal is an increasing function of temperature. A number of oscillations of...
US20140140147 STATIC RANDOM ACCESS MEMORY CIRCUIT WITH STEP REGULATOR  
Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (SRAM) component of a very large scale integration (VLSI) design, such as a...
US20140204688 REFERENCE CURRENT DISTRIBUTION  
Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a...
US20130121065 DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN SRAM  
A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair...
US20120127799 WRITE-PRECOMPENSATION AND VARIABLE WRITE BACKOFF  
A technique for writing data is disclosed. The technique includes estimating an amount of additional voltage on a victim cell of a solid-state storage device caused by writing to one or more other...
US20090121215 SYSTEMS, DEVICES, AND METHODS FOR ANALOG PROCESSING  
A system employs a plurality of physical qubits, each having a respective bias operable to up to six differentiable inputs to solve a Quadratic Unconstrained Binary Optimization problem. Some...
US20070002619 BISTABLE MULTIVIBRATOR WITH NON-VOLATILE STATE STORAGE  
The non-volatile memory cell has a volatile memory means for storing an item of binary information. Furthermore, the memory cell comprises only a single programmable resistance element for...
US20120294090 Current-Sense Amplifier With Low-Offset Adjustment and Method of Low-Offset Adjustment Thereof  
A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias...
US20070008770 STORAGE DEVICES AND SEMICONDUCTOR DEVICES  
The present invention provides a storage device including a storage element, a circuit element, and write control means. The storage element has a characteristic exhibiting a resistance changing...
US20100322005 REDUCED PROGRAMMING PULSE WIDTH FOR ENHANCED CHANNEL BOOSTING IN NON-VOLATILE STORAGE  
Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter...
US20110082963 POWER INTERRUPT MANAGEMENT  
The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead...
US20100157707 Sense Amplifier with Redundancy  
A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch...
US20060018182 Solid state microoptoelectromechanical system (moens) for reading photonics diffractive memory  
The present invention comprises a solid-state system for reading information from a photonics diffractive memory. An acousto-optic deflector directs a convergent light beam onto a micr-mirror...
US20110280059 ALTERNATING BIPOLAR FORMING VOLTAGE FOR RESISTIVITY-SWITCHING ELEMENTS  
A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and may...
US20090086524 PROGRAMMABLE ROM USING TWO BONDED STRATA AND METHOD OF OPERATION  
A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The...
US20050237800 Sector protection circuit for non-volatile semiconductor memory, sector protection method and non-volatile semiconductor memory  
A sector protection circuit of the invention has a non-volatile storage section storing data indicating sector protection/unprotection for each sector or each sector group, and a volatile storage...
US20100296334 6T SRAM Cell with Single Sided Write  
An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell...
US20070030718 Magnetic logic system  
A driving system and method to effect propagation of a magnetic domain wall through a ferromagnetic conduit are described, wherein oscillating electrical current is passed through the conduit from...
US20080123444 Adaptive memory calibration using bins  
An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a...