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US20110013445 Bias Temperature Instability-Influenced Storage Cell  
In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line...
US20140293679 MANAGEMENT OF SRAM INITIALIZATION  
An embodiment of the current disclosure is directed to a Static Random Access Memory (SRAM) device, and a design structure for the SRAM device. The SRAM device may include one or more SRAM cells....
US20120008443 IMPLEMENTING SMART SWITCHED DECOUPLING CAPACITORS TO EFFICIENTLY REDUCE POWER SUPPLY NOISE  
A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject...
US20050105374 Media diary application for use with digital device  
A media diary application implemented in a digital communication device. The media diary combines the benefit of an electronic calendar planner with a digital media file manager that organizes...
US20130094314 SRAM POWER REDUCTION THROUGH SELECTIVE PROGRAMMING  
A method of programming a memory array having plural subarrays is disclosed. (FIG. 3). The method comprises determining a minimum operating voltage (Vmin) for each subarray of the plural subarrays...
US20140286101 BACK BIAS DURING PROGRAM VERIFY OF NON-VOLATILE STORAGE  
Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during...
US20130163308 METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT, METHOD OF INITIALIZING VARIABLE RESISTANCE ELEMENT, AND NONVOLATILE STORAGE DEVICE  
Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of...
US20090267636 Security circuit having an electrical fuse ROM  
A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an...
US20110085396 REPAIR FUSE DEVICE  
A repair fuse device is provided. The repair fuse device remarkably reduces the number of the enable fuse cuttings by making initial states of all repair fuse sets to a repair state, cutting an...
US20140307516 BIAS SENSING IN DRAM SENSE AMPLIFIERS THROUGH VOLTAGE-COUPLING/DECOUPLING DEVICE  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
US20110157962 BIAS SENSING IN DRAM SENSE AMPLIFIERS THROUGH VOLTAGE-COUPLING/DECOUPLING DEVICE  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
US20060187700 Single event effect (SEE) tolerant circuit design strategy for SOI type technology  
A method of designing an integrated circuit to be Single Event Upset (SEU) immune by converting one or more Single Event Transient (SET) sensitive transistors into at least two serially connected...
US20090180340 SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING COLUMN REDUNDANCY FUSE BLOCK  
A semiconductor integrated circuit includes a semiconductor chip having an edge area and a bank area located an inner portion of the edge area, and a column redundancy fuse block disposed in the...
US20080074937 Semiconductor memory device having precharge signal generator and its driving method  
A semiconductor memory device includes a drive clock supplier and a signal generator. The drive clock supplier supplies a drive clock which is obtained by dividing an internal clock with a divide...
US20130033950 APPARATUS AND METHOD FOR REFRESHING DRAM  
A refresh method for DRAM is provided, in which a memory cell array is arranged to have multiple storing pages. Each storing page has a counter value. The method includes detecting out a portion...
US20140307499 BOOSTER CIRCUIT  
A booster circuit configured to boost a supplied voltage and provide a booster circuit output includes: an oscillator circuit configured to generate a clock signal; a charge pump circuit...
US20090303807 Semiconductor device and semiconductor system having the same  
A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a...
US20130343114 PROGRAMMED-STATE DETECTION IN MEMRISTOR STACKS  
A method for programmed-state detection in memristor stacks includes applying a first secondary switching voltage across a memristor stack to produce a first programmed-state-dependent secondary...
US20150243363 ADJUSTING LOG LIKELIHOOD RATIO VALUES TO COMPENSATE MISPLACEMENT OF READ VOLTAGES  
An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the...
US20130329490 METHOD OF SWITCHING OUT-OF-PLANE MAGNETIC TUNNEL JUNCTION CELLS  
A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through...
US20120120708 METHOD OF SWITCHING OUT-OF-PLANE MAGNETIC TUNNEL JUNCTION CELLS  
A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through...
US20140071741 OTP CELL WITH REVERSED MTJ CONNECTION  
A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming....
US20120026794 Method and apparatus of operating a non-volatile DRAM  
A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an...
US20140153325 BODY VOLTAGE SENSING BASED SHORT PULSE READING CIRCUIT  
As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and...
US20110149670 Spin valve device including graphene, method of manufacturing the same, and magnetic device including the spin valve device  
Provided are a spin valve device including graphene, a method of manufacturing the spin valve device, and a magnetic device including the spin valve device. The spin valve device may include at...
US20080272807 Thin film logic device and system  
Thin film logic circuits employ thin-film switching devices to execute complementary logic functions. Such logic devices operate, as complementary metal oxide semiconductor (CMOS) logic devices...
US20150200363 RESISTIVE SWITCHING ELEMENT AND USE THEREOF  
A bipolar resistive switching device (RSM device, FIG. 35) comprises an electrically conductive bottom electrode (BE, FIG. 35); a stack of transition metal oxides layers (RSM, FIG. 35), a number...
US20140036601 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE  
A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing...
US20130223155 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE  
A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing...
US20110026346 SELF-TIMED LOW POWER SENSE AMPLIFIER  
A sense amplifier is disclosed comprising a first sense input, a second sense input, a latch, a first p-channel control transistor arranged to electrically power a first section of the latch and...
US20110216618 VOLTAGE COMPENSATED TRACKING CIRCUIT IN SRAM  
Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay required for generating sense amplifier...
US20080234997 Design Structure for Compensating for Variances of a Buried Resistor in an Integrated Circuit  
A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the...
US20130155767 APPARATUSES AND METHODS FOR SENSING A PHASE-CHANGE TEST CELL AND DETERMINING CHANGES TO THE TEST CELL RESISTANCE DUE TO THERMAL EXPOSURE  
A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other...
US20150055389 SELF-TIMED, SINGLE-ENDED SENSE AMPLIFIER  
An integrated circuit including a sense amplifier connected to a sense line is provided. The sense amplifier is configured to end a precharge phase of the sense line based on a state of the sense...
US20130170292 HIGH VOLTAGE TOLERANT ROW DRIVER  
A circuit is configured to supply a first gate voltage (PG1) at a first voltage bias (VP1) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP1) to a...
US20120063252 VARIABILITY RESILIENT SENSE AMPLIFIER WITH REDUCED ENERGY CONSUMPTION  
An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage...
US20130176805 METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES  
An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a...
US20090040857 INTEGRATED CIRCUIT INCLUDING DECOUPLING CAPACITORS THAT CAN BE DISABLED  
An integrated circuit includes a decoupling capacitor configured to be enabled in response to the decoupling capacitor not increasing a standby current of the integrated circuit and disabled in...
US20090179301 FUSE HAVING CUTTING REGIONS AND FUSE SET STRUCTURE HAVING THE SAME  
A fuse includes a main fuse region and a plurality of cutting regions extend from the main fuse region.
US20140241101 Word Line Driver and Related Method  
A word line driver includes a first transistor electrically connected to a first voltage supply node and a word line, a second transistor electrically connected to a second voltage supply node and...
US20120243290 MULTI-LEVEL ELECTRICAL FUSE USING ONE PROGRAMMING DEVICE  
A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse...
US20090180335 INTEGRATED CIRCUIT WITH REDUCED POINTER UNCERTAINLY  
One embodiment provides an integrated circuit including a first circuit and a second circuit. The first circuit is configured to obtain a sample of a first clock via a second clock and provide a...
US20130294186 PHASE-LOCKED LOOP AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME, AND TEST SYSTEM INCLUDING THE INTEGRATED CIRCUIT CHIP  
A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency...
US20060171200 Memory using mixed valence conductive oxides  
A memory using a mixed valence conductive oxides. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor...
US20120026784 RANDOM NUMBER GENERATOR  
According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element...
US20150016203 DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION  
A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes...
US20150098279 SENSING AMPLIFIER AND SENSING METHOD THEREOF  
A sensing amplifier comprising a clamp circuit is provided. The clamp circuit is coupled between a first node and a second node. The clamp circuit comprises a first P-type transistor having a...
US20120057407 CACHING SCHEME SYNERGY FOR EXTENT MIGRATION BETWEEN TIERS OF A STORAGE SYSTEM AND METHODS THEREOF  
A storage system according to one embodiment includes logic adapted for determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system, wherein a...
US20090185437 CLOCK-BASED DATA STORAGE DEVICE, DUAL PULSE GENERATION DEVICE, AND DATA STORAGE DEVICE  
Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement. The clock-based...
US20140254255 MRAM WTIH METAL GATE WRITE CONDUCTORS  
In one embodiment of the invention, there is provided a magnetic random access (MRAM) device. The device comprises a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and...