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US20090073797 SEMICONDUCTOR MEMORY DEVICE WITH CONTROL BLOCK SHARING ROW DECODERS  
A semiconductor memory device comprises a plurality of banks including a plurality of mat rows, respectively, wherein the mat row includes a plurality of mats disposed in a same row, row decoder...
US20090257272 REDUCED SIZE CHARGE PUMP FOR DRAM SYSTEM  
A memory system includes: a memory array, comprising a plurality of memory banks, respectively enabled by a plurality of bank enable signals; a bank selector circuit, for generating the plurality...
US20150170737 BOOSTING VOLTAGE LEVEL  
A circuit comprises a driver, a first capacitive device, and a second capacitive device. The driver has an input node, an output node, and a driver supply voltage node. The first capacitive device...
US20060245264 Computing with both lock-step and free-step processor modes  
A computer system provides for both lock-step and free-step processor modes, allowing for an effective tradeoff between performance and data integrity.
US20150194208 SRAM WORDLINE DRIVER SUPPLY BLOCK WITH MULTIPLE MODES  
A wordline driver supply block supporting multiple operation modes of a memory of a microprocessor in a device for reducing power consumption thereof.
US20070109885 Defect analysis place specifying device and defect analysis place specifying method  
A defect analysis place specifying device for specifying defect analysis places from an inspection result of produced printed wiring boards in an electronic part mounting device for mounting parts...
US20100271878 INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN  
An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon....
US20130279267 METHODS AND SYSTEMS FOR ERASE BIASING OF SPLIT-GATE NON-VOLATILE MEMORY CELLS  
Methods and systems are disclosed for erasing split-gate non-volatile memory (NVM) cells using select-gate erase voltages that are adjusted to reduce select-gate to control-gate break-down...
US20100149878 FLOTOX TYPE EEPROM  
A FLOTOX EEPROM of the invention includes: a plurality of floating gates 11 arranged in array, each having a tunnel window 12 and allowing electron injection and extraction via the tunnel window;...
US20050122796 Delayed locked loop in semiconductor memory device and its control method  
A delayed locked loop in a semiconductor memory device includes a read enable signal generating block for generating a read enable signal, wherein the read enable signal is enabled based on the...
US20090091996 Solid state semiconductor storage device with temperature control function, application system thereof and control element thereof  
A solid state semiconductor storage device with temperature control function comprises a non-volatile memory unit, a temperature sensing element, and a control unit. The temperature sensing...
US20100034025 NON-VOLATILE SEMICONDUCTOR STORAGE SYSTEM  
There is provided a non-volatile memory having electrically rewritable non-volatile memory cells arranged therein. A controller controls operation at the non-volatile memory. The non-volatile...
US20150262707 DESIGN-FOR-TEST APPARATUSES AND TECHNIQUES  
Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell,...
US20150036437 FLASH MEMORY CELL WITH CAPACITIVE COUPLING BETWEEN A METAL FLOATING GATE AND A METAL CONTROL GATE  
An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control...
US20130170289 LOW VOLTAGE WRITE TIME ENHANCED SRAM CELL AND CIRCUIT EXTENSIONS  
A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell...
US20150055424 On-The-Fly Trimmable Sense Amplifier  
A trimmable sense amplifier for use in a memory device is disclosed.
US20150029782 WIDE RANGE MULTIPORT BITCELL  
A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the...
US20150023088 APPARATUSES AND METHODS FOR SENSING FUSE STATES  
Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of...
US20140098623 APPARATUSES AND METHODS FOR SENSING FUSE STATES  
Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of...
US20130315009 PERIOD SIGNAL GENERATION CIRCUIT  
A period signal generation circuit includes a first discharger configured to discharge first current from a control node which is driven in response to a first reference voltage, and a second...
US20120299655 VOLTAGE REGULATORS, AMPLIFIERS, MEMORY DEVICES AND METHODS  
Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such...
US20110235455 VOLTAGE REGULATORS, AMPLIFIERS, MEMORY DEVICES AND METHODS  
Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such...
US20110051540 Method and structure for SRAM cell trip voltage measurement  
A parametric test circuit is disclosed (FIG. 6). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected...
US20090323383 COMPARING DATA REPRESENTATIONS TO STORED PATTERNS  
A search engine includes a storage module to store a plurality of data patterns, a plurality of busses to receive a plurality of representations of a search word, a selector corresponding to at...
US20070280024 Power-up signal generator for use in semiconductor device  
In an apparatus for generating a power-up signal, a mode register set (MRS) and other circuits are prevented from being reset, thereby providing stable circuit operation. A final power-up signal...
US20110013465 INTEGRATORS FOR DELTA-SIGMA MODULATORS  
Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected...
US20070070737 METHOD AND AUXILIARY DEVICE FOR CREATING AND CHECKING THE CIRCUIT DIAGRAM FOR A CIRCUIT WHICH IS TO BE INTEGRATED  
Method and apparatus for creating and checking a circuit diagram for a circuit which is to be integrated. On the basis of this circuit diagram, a layout for the circuit which is to be integrated...
US20070201286 INPUT CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME  
An input circuit of a semiconductor memory device includes a data strobe circuit configured to buffer a data strobe signal to generate a first internal strobe signal and to generate a second...
US20130272054 SYSTEM FOR POWERING UP VOLTAGE DOMAINS AFTER EXITING POWERDOWN EVENT  
A system for charging a low voltage power domain in a low power DRAM includes: a first capacitor, for providing a local domain power voltage supply; a first transistor, coupled to the first...
US20120140575 PROCESS TOLERANT LARGE-SWING SENSE AMPLFIER WITH LATCHING CAPABILITY  
A process-tolerant large-swing sense amplifier with latching capability includes top-array and bottom-array access. The sense amplifier provides improved tolerance to process variation, reduces...
US20070189909 Apparatus for manufacturing semiconductor devices  
Provided are apparatus and methods for manufacturing semiconductor devices and more specifically exhaust system apparatus and methods used in conjunction with a plurality of semiconductor...
US20100097875 Enhanced Power Distribution in an Integrated Circuit  
An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection...
US20090097344 SEMICONDUCTOR MEMORY TESTING DEVICE AND METHOD OF TESTING SEMICONDUCTOR USING THE SAME  
The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which...
US20090014522 ENABLING HOLOGRAPHIC MEDIA BACKWARDS COMPATIBILITY WITH DUAL-USE MEDIA CARD CONNECTOR  
A holographic read only memory card which can be coupled to and read by a card reader to which electronic read only memory cards can also be coupled to and read by the card reader is disclosed....
US20080186788 ELECTRICAL FUSE AND ASSOCIATED METHODS  
A fuse link of undoped material is connected between first and second doped material contact regions and a layer of conductive material is located above the first and second contact regions and...
US20090168574 METHOD OF DRIVING 1-TRANSISTOR TYPE DRAM HAVING AN NMOS OVERLAIN ON TOP OF AN SOI LAYER  
Driving a 1-transistor DRAM composed of an NMOS on top of a SOI layer such that the 1-transistor DRAM has a corresponding parasitic bipolar transistor component includes precharging, shifting, and...
US20140204657 SRAM VOLTAGE ASSIST  
The disclosure provides for an SRAM array having a plurality of wordlines and a plurality of bitlines, referred to generally as SRAM lines. The array has a plurality of cells, each cell being...
US20150085579 CONTACT STRUCTURE AND FORMING METHOD  
Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second...
US20120257435 NON-SALICIDE POLYSILICON FUSE  
The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming...
US20110002188 Apparatus for Nonvolatile Multi-Programmable Electronic Fuse System  
Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse...
US20090168580 FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE  
A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals...
US20060028873 Method for data-flow quality control, a related receiver and a related transmitter  
The present invention relates to a method for data-flow quality control in a Digital Subscriber Line communications system comprising a transmitter, a receiver, and a Digital Subscriber Line...
US20140078804 Mask Design With Optically Isolated Via and Proximity Correction Features  
A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define...
US20090109790 Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit  
An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the...
US20130083594 MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY  
A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined...
US20130077394 MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY  
A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined...
US20110051508 MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY  
A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined...
US20130279273 LATCH CIRCUIT, NONVOLATILE MEMORY DEVICE AND INTEGRATED CIRCUIT  
A latch circuit may include a plurality of latches configured to operate in response to power supplied to a pull-up power supply node and a pull-down power supply node, a delay unit configured to...
US20140269034 INTEGRATED CAPACITOR BASED POWER DISTRIBUTION  
An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same...
US20130258751 FRAM COMPILER AND LAYOUT  
A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM...