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US20070243620 Analysis and Screening of Solid Forms Using the Atomic Pair Distribution Function  
A method that comprises providing a PDF trace of a first sample of a substance, providing a PDF trace of a second sample of the substance, and comparing the PDF traces to determine whether the...
US20090086524 PROGRAMMABLE ROM USING TWO BONDED STRATA AND METHOD OF OPERATION  
A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The...
US20090014522 ENABLING HOLOGRAPHIC MEDIA BACKWARDS COMPATIBILITY WITH DUAL-USE MEDIA CARD CONNECTOR  
A holographic read only memory card which can be coupled to and read by a card reader to which electronic read only memory cards can also be coupled to and read by the card reader is disclosed. The...
US20110122671 Systems and methods for controlling integrated circuit operation with below ground pin voltage  
Systems and methods for controlling operation of an integrated circuit by applying below ground voltage to one or more pins of the integrated circuit, and in which the application of a below ground...
US20110255327 METHOD AND SYSTEM FOR SPLIT THRESHOLD VOLTAGE PROGRAMMABLE BITCELLS  
Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal...
US20080212354 BIASED SENSING MODULE  
A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output...
US20090296448 DIODE AS VOLTAGE DOWN CONVERTER FOR OTP HIGH PROGRAMMING VOLTAGE APPLICATIONS  
A voltage down converter for programming a one-time-programmable (OTP) memory comprising is disclosed, the voltage down converter comprises a bonding pad for coupling to a programming power supply,...
US20100188881 Method and Device for Correcting and Obtaining Reference Voltage  
The present invention discloses a method for adjusting a reference voltage, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference...
US20110007542 TESTING ONE TIME PROGRAMMING DEVICES  
A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern,...
US20070025134 Flexible OTP sector protection architecture for flash memories  
A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and...
US20110019459 Three-Dimensional Mask-Programmable Read-Only Memory with Reserved Space  
The present invention discloses a three-dimensional mask-programmable read-only memory with reserved space (3D-MPROMRS). It is released in a sequence of versions. In the original version, its...
US20120081942 TEST CELLS FOR AN UNPROGRAMMED OTP MEMORY ARRAY  
Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells...
US20100284210 One-time programmable memory cell  
According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has...
US20110317468 Non-Volatile Memory with Split Write and Read Bitlines  
Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell...
US20080205115 APPARATUS AND METHOD FOR TRIMMING INTEGRATED CIRCUIT  
A trimming apparatus including a switch transistor and a one-time programming (OTP) memory component is provided. The switch transistor has a first source/drain terminal connected to a first bias...
US20100011266 PROGRAM VERIFY METHOD FOR OTP MEMORIES  
A method for executing a program verify operation in a non-volatile memory. A data register having master and slave latching circuits is used for concurrently storing two different words of data....
US20100322010 NON-VOLATILE MEMORY PROGRAMMABLE THROUGH AREAL CAPACITIVE COUPLING  
A programmable non-volatile device is made which uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device...
US20090122604 METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING RELATED APPLICATION DATA  
A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry...
US20090086525 Multi-layered memory devices  
A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The...
US20080151135 Common voltage adjustment apparatus  
A common voltage adjustment apparatus for adjusting a common voltage of a liquid crystal display (LCD) panel includes a data-read-write circuit and an output circuit. The data-read-write circuit...
US20100244892 ROM IMPLEMENTATION FOR ROM BASED LOGIC DESIGN  
A logic device implementing configurations for ROM based logic uses arrays of memory cells to provide outputs based on inputs received at the logic device. The logic device stores values in the...
US20090237976 N-ary Three-Dimensional Mask-Programmable Read-Only Memory  
N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM) stores multi-bit-per-cell. Its memory cells can have N states (N>2) and data are stored as N-ary codes. N-3DMPROM has a larger...
US20100133968 CASING COMPRISING A RE-RECORDABLE COMPUTER MEDIUM TO BE FIXED IN A SERVICE CABINET  
The invention relates to a case 1 intended to be fixed in an electrical cabinet, said case comprising a frontal opening which can be closed by a means of closing 3, and further comprising means of...
US20060268593 Read-only memory array with dielectric breakdown programmability  
According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated...
US20090225581 Multi-bit memory device using multi-plug  
A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a...
US20090284504 MEMORY DEVICE WITH ONE-TIME PROGRAMMABLE FUNCTION, AND DISPLAY DRIVER IC AND DISPLAY DEVICE WITH THE SAME  
A display driver IC with a built-in memory device having a one-time programmable function is provided. The memory device includes: a cell array comprising a plurality of one-time programmable unit...
US20090207644 MEMORY CELL ARCHITECTURE  
Embodiments of the present invention disclose a memory architecture for optimizing memory performance and size. Memory optimization is realized by configuring the memory to a particular logic...
US20070279829 CONTROL SYSTEM FOR STATIC NEUTRALIZER  
The present invention pertains to various embodiments for managing ion current balance by independently controlling positive ion current and negative ion current generated during static...
US20100046269 Programmable read only memory  
An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is...
US20090316463 Semiconductor Device and Method for Making Same  
Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the...
US20090262565 METHOD FOR PROGRAMMING NONVOLATILE MEMORY DEVICE  
Disclosed is a method for programming a nonvolatile memory device including one time programmable unit cells. The method for programming a nonvolatile memory device including one time programmable...
US20100322001 INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING AND SEPARATE READ/WRITE PATHS  
A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through...
US20110128768 MEMORY INTERFACE CIRCUIT  
According to one embodiment, a differential circuit receives, as differential inputs, a readout signal read out from a semiconductor storage element and a reference voltage. An equalizing circuit...
US20090316464 LOW POWER READ SCHEME FOR READ ONLY MEMORY (ROM)  
A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control...
US20090231351 SEMICONDUCTOR MEMORY DEVICE HAVING DATA ROTATION/INTERLEAVE FUNCTION  
An object of the present invention is to provide a memory device and a memory application device which can reduce memories and reduce burden on processings by reading out predetermined bit data...
US20110157956 METHOD AND APPARATUS FOR INCREASING YIELD  
Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on...
US20090237974 Programmable memory cell  
A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across...
US20080008019 High Speed Read-Only Memory  
A high speed read-only memory (ROM). Data stored in a memory cell in the ROM array is provided to a sense amplifier in a differential form. Two transistors storing complementary logic states form a...
US20090323387 One-Time Programmable Memory and Operating Method Thereof  
A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer;...
US20090316465 EFFICIENT WORD LINES, BIT LINE AND PRECHARGE TRACKING IN SELF-TIMED MEMORY DEVICE  
A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of...
US20090251942 METHOD OF PROGRAMMING A MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE AND INTEGRATED CIRCUIT INCORPORATING SUCH A MEMORY  
A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access...
US20090237973 Design method for read-only memory devices  
A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data...
US20090262567 NONVOLATILE MEMORY DEVICE  
A nonvolatile memory device including one-time programmable (OTP) unit cell is provided. The nonvolatile memory device includes: a unit cell; a detecting unit configured to detect data from the...
US20120044738 ONE-TIME PROGRAMMABLE MEMORIES USING POLYSILICON DIODES AS PROGRAM SELECTORS  
Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via...
US20090303769 ROM ARRAY WITH SHARED BIT-LINES  
Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the...
US20100259965 HIGH SPEED OTP SENSING SCHEME  
A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge...
US20100188880 POWER SWITCHING FOR PORTABLE APPLICATIONS  
A voltage generation and power switching apparatus, method and system is described. The apparatus includes a digital media processing chip. The digital media processing chip includes a control...
US20080198643 One-time programmable cell and memory device having the same  
One-time programmable cell and memory device having the same includes a first metal oxide semiconductor (MOS) transistor configured to form a current path between a first node and a second node in...
US20120008363 Diode-Less Array for One-Time Programmable Memory  
A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction...
US20100272265 SYSTEM AND METHOD TO CONTROL ONE TIME PROGRAMMABLE MEMORY  
Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method...
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