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US20090287362 MONITORED BURN-IN TEST APPARATUS AND MONITORED BURN-IN TEST METHOD  
A monitored burn-in test method includes: subjecting an element set, including elements, to a writing process for writing data into each of the elements, the elements requiring a refresh process;...
US20090285006 Semiconductor Memory and Method for Operating a Semiconductor Memory  
A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element...
US20090279373 AUTO-REFRESH OPERATION CONTROL CIRCUIT FOR REDUCING CURRENT CONSUMPTION OF SEMICONDUCTOR MEMORY APPARATUS  
An auto-refresh operation control circuit for a semiconductor memory apparatus is activated according to a bank active signal for executing a refresh operation and terminates the refresh operation...
US20090273970 MEMORY DEVICE INCLUDING A PROGRAMMABLE RESISTANCE ELEMENT  
Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface...
US20090268539 Chip, Multi-Chip System in a Method for Performing a Refresh of a Memory Array  
A chip includes a memory array and a refresh counter. The refresh counter is configured to receive refresh trigger signals. The refresh counter is configured or configurable to initiate a refresh...
US20090268537 Semiconductor memory device  
A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of...
US20090257299 SOFTWARE REFRESHED MEMORY DEVICE AND METHOD  
A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the...
US20090257273 2T SRAM CELL STRUCTURE  
A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word...
US20090251985 SEMICONDUCTOR MEMORY APPARATUS  
A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the...
US20090251982 Low Energy Memory Component  
The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply...
US20090245004 SEMICONDUCTOR DEVICE INCLUDING MULTI-CHIP  
In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package....
US20090238021 Semiconductor memory device and operation method therefor  
Disclosed herein is a semiconductor memory device, including: a memory array section wherein a memory array which requires a refresh operation is formed; an interface section configured to carry...
US20090238020 INTEGRATED CIRCUIT INCLUDING MEMORY REFRESHED BASED ON TEMPERATURE  
An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured...
US20090238015 Appartus and method for controlling refresh with current dispersion effect in semiconductor device  
A refresh control apparatus is provided which is capable of dispersing a peak current at an all-bank refresh mode and reducing the characteristic difference between the banks. The refresh control...
US20090225623 METHOD, DEVICE AND SYSTEM FOR REDUCING THE QUANTITY OF INTERCONNECTIONS ON A MEMORY DEVICE  
Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an...
US20090225620 SEMICONDUCTOR MEMORY APPARATUS  
A semiconductor memory apparatus includes: a compensation voltage input node; a core voltage generator configured to generate a core voltage using an external power source voltage and supply the...
US20090225617 SYSTEM AND METHOD FOR HIDDEN-REFRESH RATE MODIFICATION  
A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first...
US20090225616 MEMORY THAT RETAINS DATA WHEN SWITCHING PARTIAL ARRAY SELF REFRESH SETTINGS  
A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to...
US20090219775 Semiconductor memory device  
Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by...
US20090213675 SEMICONDUCTOR MEMORY DEVICE  
A memory includes memory cells, wherein in a first cycle of writing first logic data, sense amplifiers apply a first potential to bit lines, drivers apply a second potential to a selected word line...
US20090201757 SEMICONDUCTOR DEVICE  
Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon...
US20090201751 SEMICONDUCTOR DEVICE IN WHICH A MEMORY ARRAY IS REFRESHED BASED ON AN ADDRESS SIGNAL  
In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and Nε2 holds) in a single refresh...
US20090201723 Single Transistor Memory Cell  
A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises...
US20090185440 ACTIVE CYCYLE CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS  
An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh...
US20090180342 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF  
A memory including; cells, wherein a refresh operation includes a first refresh and a second refresh, in the first refresh, a first potential higher than a gate potential in a retention is applied...
US20090175098 SEMICONDUCTOR MEMORY DEVICE INCLUDING FLOATING BODY TRANSISTOR MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME  
A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers...
US20090168571 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF  
Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes:...
US20090168520 3T high density NVDRAM cell  
A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.
US20090161469 SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM  
The semiconductor integrated circuit comprises: a first buffer circuit that outputs a first output signal to an output terminal on receipt of a first input signal; a second buffer circuit that...
US20090161468 SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND MEMORY ACCESS CONTROL METHOD  
A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for...
US20090161467 MEMORY DEVICE AND REFRESH METHOD THEREOF  
A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined...
US20090161466 EXTENDING FLASH MEMORY DATA RETENSION VIA REWRITE REFRESH  
Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a...
US20090161459 Dynamic Random Access Memory With Low-Power Refresh  
A technique to reduce refresh power in a DRAM is disclosed. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second...
US20090161457 Semiconductor storage device having redundancy area  
A semiconductor storage device is provided with: a memory cell array which includes a normal area and a redundancy area which replaces a defective memory cell in the normal area; a normal area...
US20090161456 Semiconductor memory device which delays refreshment signal for performing self-refreshment  
A semiconductor memory device having two refreshment modes of auto-refreshment and partial self-refreshment imposed on memory cells includes a command decoder which detects one of the refreshment...
US20090154279 REFRESH PERIOD SIGNAL GENERATOR WITH DIGITAL TEMPERATURE INFORMATION GENERATION FUNCTION  
A refresh period signal generator with a digital temperature information generation function includes a temperature information generating part configured to generate temperature information by...
US20090154278 MEMORY DEVICE WITH SELF-REFRESH OPERATIONS  
An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row...
US20090154277 METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RELATED MEMORY  
The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line...
US20090154276 Auto-refresh controlling apparatus  
An auto-refresh control apparatus is provided which includes a counter unit for outputting counter signals in response to an external auto-refresh command signal, and a refresh command signal...
US20090147608 POWER MANAGEMENT CONTROL AND CONTROLLING MEMORY REFRESH OPERATIONS  
A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete...
US20090147607 RANDOM ACCESS MEMORY AND DATA REFRESHING METHOD THEREOF  
A random access memory and a data refreshing method thereof are provided. The random access memory includes a memory array having a plurality of word lines; a control logic unit which is used for...
US20090141576 METHOD OF REFRESHING DATA IN A STORAGE LOCATION  
An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The...
US20090141575 Method and Apparatus for Idle Cycle Refresh Request in Dram  
Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed...
US20090135660 Apparatus, memory device and method of improving redundancy  
An apparatus includes a memory device. The memory device includes a first memory cell column which includes a plurality of first memory cells, a second memory cell column including a plurality of...
US20090109784 Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same  
An access area is set within an address space of a dynamic random access memory by arranging two or more complete columns of blocks, in which blocks of memory cells are arranged within an entirety...
US20090109783 Refresh controlling circuit  
A refresh controlling circuit includes an MRS latch unit configured to output a mask information signal of a bank and a mask information signal of a segment by synchronizing a first address signal...
US20090109782 TEMPERATURE DETECTOR IN AN INTEGRATED CIRCUIT  
A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage...
US20090109773 SEMICONDUCTOR DEVICE AND REFRESH METHOD  
In order to successively perform refresh operations, a semiconductor device has a plurality of regions performing a repair independently from each other, even when the repair is carried out in the...
US20090109755 Neighbor block refresh for non-volatile memory  
Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a...
US20090103384 APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS  
A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored...
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