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US20090310432 BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE  
In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver....
US20090303820 APPARATUS AND METHOD FOR LOW POWER SENSING IN A MULTI-PORT SRAM USING PRE-DISCHARGED BIT LINES  
A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the...
US20090303777 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural...
US20090303821 Apparatus and Method for Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Discharged Bit Lines  
An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory...
US20090303812 PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS  
A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock...
US20090303819 WRITE AND READ ASSIST CIRCUIT FOR SRAM WITH POWER RECYCLING  
A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge...
US20090303804 SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME  
A semiconductor device includes an overdriving control circuit configured to generate a first drive signal and a second drive signal in response to an internal signal of an active command mode, an...
US20090303822 BIT LINE EQUALIZING CONTROL CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS  
A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit...
US20090296488 High Speed Sense Amplifier Array and Method for Nonvolatile Memory  
Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented....
US20090296460 SEMICONDUCTOR MEMORY DEVICE  
The present invention provides a semiconductor memory device capable of preventing erroneous writing of a data signal. In DL drivers of an MRAM, transistors corresponding to a selected digit line...
US20090290431 NONVOLATILE MEMORY DEVICE  
A nonvolatile memory device includes a page buffer circuit. The page buffer circuit includes a memory cell area, a first bit line select unit, and a second bit line select unit. A plurality of...
US20090290432 METHOD OF READING DATA IN A NON-VOLATILE MEMORY DEVICE  
A method of reading data in a non-volatile memory device compensates for a change in a reading/verifying result in accordance with a change of temperature. The method includes sensing a temperature...
US20090285032 Self pre-charging and equalizing bit line sense amplifier  
A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit...
US20090285009 Nonvolatile memory devices using variable resistive elements  
A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory...
US20090285040 Semiconductor Memory Device  
A semiconductor memory device includes a memory cell array. The memory cell array includes a plurality of sub arrays. Each sub array includes a plurality of memory cells. The memory cell includes a...
US20090279348 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device comprises a memory cell array, which includes a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged...
US20090279373 AUTO-REFRESH OPERATION CONTROL CIRCUIT FOR REDUCING CURRENT CONSUMPTION OF SEMICONDUCTOR MEMORY APPARATUS  
An auto-refresh operation control circuit for a semiconductor memory apparatus is activated according to a bank active signal for executing a refresh operation and terminates the refresh operation...
US20090273989 Synchronous Command Base Write Recovery Time Auto Precharge Control  
Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A...
US20090273994 DUAL MODE ACCESSING SIGNAL CONTROL APPARATUS AND DUAL MODE TIMING SIGNAL GENERATING APPARATUS  
A dual mode accessing signal control apparatus for being used in a dummy cells set of a memory, and a dual mode timing signal generating apparatus comprising a dual mode accessing signal control...
US20090273997 Controlling Apparatus and Controlling Method for Controlling a Pre-Charge Activity on a SRAM Array  
A controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array are provided. The controlling apparatus comprises: a detecting module, a controlling module...
US20090273988 CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES  
According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge...
US20090268535 SEMICONDUCTOR DEVICE GUARANTEEING STABLE OPERATION  
A semiconductor device includes a data line pair formed of a data line and a complementary data line; a first sensing amplification unit including a first sensing amplifier and a second sensing...
US20090268534 SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF  
A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a...
US20090268536 Precharge voltage supply circuit and semiconductor device using the same  
A precharge voltage supply circuit and a semiconductor device using the same are disclosed. The semiconductor device includes a first comparator for comparing a precharge voltage with a first...
US20090262587 Semiconductor memory device  
A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a...
US20090262568 SEMICONDUCTOR MEMORY DEVICE  
A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is...
US20090257293 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier...
US20090257288 APPARATUS AND METHOD FOR INCREASING DATA LINE NOISE TOLERANCE  
Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line...
US20090257290 LOW POWER SHIFT REGISTER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME  
A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit...
US20090251979 METHOD FOR SUPPRESSING CURRENT LEAKAGE IN MEMORY  
A method for suppressing a current leakage of a memory is provided. The memory at least includes a memory cell, an equalizing circuit, a current limiter, a word line and a pair of complementary bit...
US20090251980 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a discharge circuit that discharges bit lines to a ground potential, a sense amplifier of a single-ended input configuration, and a charging transistor...
US20090251943 TEST CIRCUIT FOR AN UNPROGRAMMED OTP MEMORY ARRAY  
Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate...
US20090244955 SEMICONDUCTOR STORAGE DEVICE  
This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit...
US20090244950 SEMICONDUCTOR MEMORY DEVICE HIGHLY INTEGRATED IN DIRECTION OF COLUMNS  
First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read...
US20090238019 Bit line precharge circuit having precharge elements outside sense amplifier  
A bit line precharge circuit capable of improving bit line precharge operation includes a first precharge element for precharging a first bit line in response to a first precharge signal, a...
US20090231938 METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE  
A method of operating a non-volatile memory device reduces a time for discharging a precharged voltage when a program operation or a read operation is performed, thereby decreasing a total...
US20090231904 FERROELECTRIC MEMORY WITH SUB BIT-LINES CONNECTED TO EACH OTHER AND TO FIXED POTENTIALS  
A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting...
US20090231939 Circuit and Method for a Vdd Level Memory Sense Amplifier  
A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense...
US20090231931 LOW POWER MEMORY ARCHITECTURE  
A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power...
US20090231903 FERROELECTRIC MEMORY AND METHOD FOR TESTING THE SAME  
A driver circuit and a precharge circuit apply, in a test mode, a fixed potential to a bit-line, while applying a second plate-line voltage to a plate-line. Then, the bit-line is switched from a...
US20090231934 Advanced Bit Line Tracking in High Performance Memory Compilers  
A method accurately tracks a bit line maturing time for compiler memory. The method includes enabling a dummy word line in response to an internal clock signal. The dummy word line is enabled prior...
US20090225613 TWIN CELL ARCHITECTURE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND THOSE DEVICES INCORPORATING EMBEDDED DRAM  
A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell...
US20090225623 METHOD, DEVICE AND SYSTEM FOR REDUCING THE QUANTITY OF INTERCONNECTIONS ON A MEMORY DEVICE  
Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an...
US20090225584 RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT IN SERIES WITH STORAGE CAPACITOR  
Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor is described herein. Embodiments may include memory devices and systems that have plurality of...
US20090219767 PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES  
A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access...
US20090219768 SEMICONDUCTOR MEMORY DEVICE HAVING SHARED BIT LINE SENSE AMPLIFIER SCHEME AND DRIVING METHOD THEREOF  
A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit...
US20090213673 Data processor memory circuit  
A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a...
US20090213674 Method and device for controlling a memory access and correspondingly configured semiconductor memory  
Method and device for controlling a memory access and correspondingly configured semiconductor memory A method and a device for controlling a memory access of a memory comprising memory cells are...
US20090201747 MEMORY, BIT-LINE PRE-CHARGE CIRCUIT AND BIT-LINE PRE-CHARGE METHOD  
A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp...
US20090201730 Method and apparatus of operating a non-volatile DRAM  
A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an...
Matches 1 - 50 out of 199 1 2 3 4 >