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US20100091539 SOLID STATE DEVICE PRODUCTS, INTERMEDIATE SOLID STATE DEVICES, AND METHODS OF MANUFACTURING AND TESTING THE SAME  
Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test...
US20140126312 SENSE AMPLIFIER SOFT-FAIL DETECTION CIRCUIT  
Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier,...
US20060050580 Method for generating identification code of semiconductor device, method for identifying semiconductor device and semiconductor device  
A semiconductor device including memory cells such as flip-flops, RAMs or SRAMs is powered on, and first logic signals of Hi or Lo output from the respective memory cells are obtained. A...
US20140043927 METHOD FOR OPTIMIZING REFRESH RATE FOR DRAM  
A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating...
US20100091596 SOLID STATE DRIVE SYSTEMS AND METHODS OF REDUCING TEST TIMES OF THE SAME  
Example embodiments of the inventive concept are directed to solid state device systems and methods of reducing test times of the same.
US20110242919 Precharge Voltage Supplying Circuit  
A precharge voltage supplying circuit comprises a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is...
US20080080277 Method and system of analyzing failure in semiconductor integrated circuit device  
A method of analyzing a failure in a semiconductor integrated circuit device may include storing defects and analog characteristics correlated with the defects in a database, detecting a fail bit...
US20100329055 MEASURING ELECTRICAL RESISTANCE  
A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that...
US20150029799 CANARY CIRCUIT WITH PASSGATE TRANSISTOR VARIATION  
A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. Each bitcell has at least a passgate...
US20100296329 Differential Plate Line Screen Test for Ferroelectric Latch Circuits  
Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled...
US20080273408 SYSTEM FOR BITCELL AND COLUMN TESTING IN SRAM  
A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the...
US20110158018 Structure and Methods for Measuring Margins in an SRAM Bit  
Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In...
US20100008170 Semiconductor tester and testing method of semiconductor memory  
The disclosure concerns a semiconductor tester for testing a memory under test. The semiconductor tester comprises a pattern generator generating address information on the pages and generating a...
US20090207673 SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI TEST  
A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches...
US20120075919 Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability  
Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and...
US20150255174 MEMORY TESTING METHOD AND APPARATUS  
A method and an apparatus for testing a memory are provided, where the memory includes a plurality of sectors each of which includes a plurality of bytes, and the testing is performed to the...
US20140063997 DRAM REFRESH  
A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast...
US20090109774 TEST METHOD AND SEMICONDUCTOR DEVICE  
A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test...
US20070171741 METHOD OF CURING ANALOG DEVICE FAIL THROUGH FAST TRANSISTOR  
Disclosed is a method of curing a failure of an analog device, wherein the operational range of a transistor is optimized, thereby curing a failure in the analog device and enhancing a yield. In...
US20110013470 Structure and Method for Screening SRAMS  
An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and...
US20090046524 MULTI-COLUMN DECODER STRESS TEST CIRCUIT  
The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by...
US20060164894 Enabling test modes of individual integrated circuit devices out of a plurality of integrated circuit devices  
Methods and apparatus are provided. A common test-mode enable signal is received at two or more integrated circuit devices of an electronic system. A test mode of only an integrated circuit device...
US20080259695 Semiconductor Memory Devices Having a Demultiplexer and Related Methods of Testing Such Semiconductor Memory Devices  
A semiconductor memory device includes a memory cell array and a demultiplexer that has a first input port that is configured to receive both an address signal and a data signal and a second input...
US20070258298 Parallel programming of flash memory during in-circuit test  
A method and system for parallel programming flash devices during in-circuit testing is described. A parallel processing device is located in a test fixture of an In-Circuit Tester (ICT) for each...
US20110051540 Method and structure for SRAM cell trip voltage measurement  
A parametric test circuit is disclosed (FIG. 6). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected...
US20090097344 SEMICONDUCTOR MEMORY TESTING DEVICE AND METHOD OF TESTING SEMICONDUCTOR USING THE SAME  
The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which...
US20070127300 Bun-in test method semiconductor memory device  
A semiconductor memory device includes a switch circuit that inverts input data or output data when burn-in mode enable signals are activated or a control signal switch that inverts external...
US20090323445 High Performance Read Bypass Test for SRAM Circuits  
A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in...
US20090231901 SEMICONDUCTOR INTEGRATED CIRCUIT FOR SUPPORTING A TEST MODE  
A semiconductor integrated circuit for supporting a test mode includes a program region including at least one One Time Programmable Cell Array, and a program region control unit configured to...
US20060197573 Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit  
The semiconductor integrated circuit of the present invention comprises a clock circuit for generating a clock signal. The clock circuit comprises a clock control circuit for controlling...
US20100232242 Method for Constructing Shmoo Plots for SRAMS  
A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array...
US20080077830 Internal signal monitoring device in semiconductor memory device and method for monitoring the same  
An internal signal monitoring device in a semiconductor memory device includes: an internal signal input unit to receive an internal signal to be monitored and having an output to provide a...
US20090231933 SEMICONDUCTOR MEMORY DEVICE WITH SIGNAL ALIGNING CIRCUIT  
A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in...
US20130058178 SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUITS BY DETERMINING THE SOLID TIMING WINDOW  
Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, the solid timing window used to determine a key timing index. The key timing index...
US20090323417 SEMICONDUCTOR MEMORY REPAIRING A DEFECTIVE BIT AND SEMICONDUCTOR MEMORY SYSTEM  
A semiconductor memory has a plurality of blocks, and each of the blocks comprises a plurality of pages, and further, each of the pages has a plurality of memory cells. A block having defective...
US20100034037 Semiconductor testing device and method of testing semiconductor memory  
The disclosure concerns a semiconductor tester for testing a MUT, comprising a pattern generator; a pattern formatter; a comparator comparing a result signal from the MUT with an expectation...
US20110273946 UNIVERSAL TEST STRUCTURES BASED SRAM ON-CHIP PARAMETRIC TEST MODULE AND METHODS OF OPERATING AND TESTING  
An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to...
US20090190416 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR STORAGE DEVICE  
A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality...
US20080062786 APPARATUS AND METHOD FOR PROVIDING ATOMICITY WITH RESPECT TO REQUEST OF WRITE OPERATION FOR SUCCESSIVE SECTOR  
An apparatus for providing atomicity with respect to a request of a write operation for successive sectors in a flash memory is provided. The apparatus includes a data write module writing data in...
US20090109756 MEMORY DEVICE WITH VARIABLE TRIM SETTING  
A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim...
US20060002208 Housing for a semiconductor device and semiconductor device testing system for testing the contacting for semiconductor devices positioned one above the other  
The invention relates to a housing for a semiconductor device and a novel semiconductor device testing system, in particular for testing the contacting of semiconductor devices positioned one...
US20080186785 Semiconductor memory device for preventing supply of excess specific stress item and test method thereof  
A semiconductor memory device includes a memory core which receives a specific stress item and a pattern item from an external source, a switch part which provides the power supplied from an...
US20100091595 INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST  
An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of...
US20100061168 FUSES FOR MEMORY REPAIR  
Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of...
US20130021864 Array Power Supply-Based Screening of Static Random Access Memory Cells for Bias Temperature Instability  
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors...
US20080304344 Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device  
A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device...
US20090257296 Programmable memory repair scheme  
The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a...
US20140301143 TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY  
In operation, respective lifetime expectancy scores are calculated for each of a plurality of blocks of a memory based on a respective count percentage of free space of each of the blocks. The...
US20110090751 SYSTEMS AND METHODS FOR EFFICIENTLY REPAIRING DYNAMIC RANDOM-ACCESS MEMORY HAVING MARGINALLY FAILING CELLS  
A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the...
US20090067259 SEMICONDUCTOR MEMORY DEVICE CONFIGURED TO REDUCE CURRENT CONSUMPTION ASSOCIATED WITH CRITICAL EVALUATING OF DATA WRITE OPERATIONS  
A semiconductor memory device that utilizes a routing controller and various specific operational modes for reducing current consumption during data write pass operations. The semiconductor memory...