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US20080117694 Semiconductor device and semiconductor chips  
High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b...
US20120170385 OUTPUT DRIVER AND ELECTRONIC SYSTEM COMPRISING SAME  
An output driver comprises a pull-up circuit that pulls up an output node to a supply voltage in N successive intervals in response to N pull-up control signals having different phases and a...
US20090303808 SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF  
A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal...
US20080291757 SIGNAL MASKING METHOD, SIGNAL MASKING CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT  
A signal masking circuit includes a detection circuit, a delayed read data strobe signal generation circuit, a gating circuit, a counting circuit, and a masking circuit. The detection circuit...
US20090273985 SEMICONDUCTOR DEVICE HAVING MULTIPLE I/O MODES  
Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller...
US20070201286 INPUT CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME  
An input circuit of a semiconductor memory device includes a data strobe circuit configured to buffer a data strobe signal to generate a first internal strobe signal and to generate a second...
US20060209619 Data input circuit of synchronous semiconductor memory device using data sampling method for changing DQS domain to clock domain  
Provided is a data input circuit of a semiconductor memory device. The data input circuit includes: an input buffer that samples an external data signal in response to a data strobe signal and...
US20100091591 DATA STROBE SIGNAL GENERATING DEVICE AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME  
A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first clock signal and disabled in synchronization...
US20100054056 MEMORY ACCESS STROBE CONFIGURATION SYSTEM AND PROCESS  
A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a...
US20070291557 STACKED SEMICONDUCTOR DEVICE  
Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural...
US20090129179 VARIABLE DELAY CIRCUIT, MEMORY CONTROL CIRCUIT, DELAY AMOUNT SETTING APPARATUS, DELAY AMOUNT SETTING METHOD AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH DELAY AMOUNT SETTING PROGRAM IS RECORDED  
A variable delay circuit being able to change a delay amount from when a signal is inputted to when the signal is outputted has a first delay section delaying the signal by a first delay amount, a...
US20090154285 MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK  
A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a...
US20100067315 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD THEREOF  
A semiconductor IC device includes a common column signal generating block providing precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality...
US20090207668 DATA STROBE CLOCK BUFFER IN SEMICONDUCTOR MEMORY APPARATUS, METHOD OF CONTROLLING THE SAME, AND SEMICONDUCTOR APPARATUS HAVING THE SAME  
A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate...
US20080012615 Delay locked loop, semiconductor memory device including the same, and method of generating delay clock signals  
A delay locked loop may include a period locked loop portion. The period locked loop portion may include a delay. The delay may include an even number of delay cells dependently connected in the...
US20090161453 METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM  
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory...
US20070206428 HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF  
A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data...
US20090154266 SEMICONDUCTOR INTEGRATED CIRCUIT, MEMORY SYSTEM AND ELECTRONIC IMAGING DEVICE  
A semiconductor integrated circuit (100) fetches read data from DDR-SDRAMs (110, 120) each operating in synchronization with a clock, and transfers the read data. The semiconductor integrated...
US20090109770 SEMICONDUCTOR DEVICE WITH DDR MEMORY CONTROLLER  
In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection...
US20100296351 TIMING ADJUSTMENT CIRCUIT, TIMING ADJUSTMENT METHOD, AND CORRECTION VALUE COMPUTING METHOD  
A timing adjustment circuit includes a determination unit for outputting delay information corresponding to a period of a first input signal, a storing unit for storing a plurality of correction...
US20090244994 Data strobe signal generating circuit capable of easily obtaining valid data window  
A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal,...
US20090285042 Memory interface circuit and memory system including the same  
The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave...
US20060245265 Memory control system  
The memory control system includes a memory unit, bus master(s), arbiter, and memory controller. The bus masters output bus use request signals, block mode signals, block information, and drive...
US20080025115 METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR MEMORY DEVICE USING INTERNAL CLOCK SIGNAL OF SEMICONDUCTOR MEMORY DEVICE AS DATA STROBE SIGNAL  
Provided are a method and system for testing a semiconductor memory device using an internal clock signal of the semiconductor memory device as a data strobe signal. The internally-generated data...
US20090086557 SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME  
A synchronous semiconductor memory device including a data alignment reference pulse generating unit configured to generate a data alignment reference pulse in response to a data strobe signal...
US20100039870 MEMORY CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCORPORATING THE SAME  
A memory control circuit includes a clock generation circuit that generates a clock signal and provides the clock signal to an external memory device, and at least one retention circuit that...
US20080239843 INTERFACE CIRCUIT, MEMORY INTERFACE SYSTEM, AND DATA RECEPTION METHOD  
An interface circuit is disclosed that can include a delay circuit that generates a delay signal obtained by delaying a data strobe signal; a first logical circuit that performs a logical operation...
US20090161454 RINGING MASKING DEVICE HAVING BUFFER CONTROL UNIT  
A ringing masking device includes a data strobe buffer unit buffering a data strobe signal and outputting a rising pulse and a falling pulse synchronized with a buffer signal. A buffer control unit...
US20080205170 DDR-SDRAM INTERFACE CIRCUITRY, AND METHOD AND SYSTEM FOR TESTING THE INTERFACE CIRCUITRY  
According to one aspect of an embodiment of the present invention, there is provided a memory interface circuit including a first data output circuit which outputs a data signal based on a data...
US20100014365 DATA INPUT CIRCUIT AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME  
A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe...
US20100039875 Strobe Acquisition and Tracking  
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory...
US20110299347 DYNAMIC DETECTION OF A STROBE SIGNAL WITHIN AN INTEGRATED CIRCUIT  
A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the...
US20080144405 Data strobe timing compensation  
A method, apparatus, and system are disclosed. In one embodiment, the method receiving data from a memory on a first interconnect of at least one interconnect, receiving a source-synchronous data...
US20120262997 METHOD FOR SEARCHING OPTIMUM VALUE OF MEMORY  
A method for searching an optimum value of a memory includes the following steps. A first and a second phase delay values of the memory are sequentially set to a plurality of first values and a...
US20090273992 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF  
A semiconductor device includes a pad configured to receive a data strobe signal, and a path selector configured to output the data strobe signal through a corresponding input path during a normal...
US20100067314 Memory Systems And Methods For Dynamically Phase Adjusting A Write Strobe And Data To Account For Receive-Clock Drift  
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write...
US20100061165 Circuitry and Methods for Improving Differential Signals That Cross Power Domains  
Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain boundary along the output paths that...
US20090273993 SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF  
A semiconductor memory device that generates a data strobe reset signal for preventing ring-back of a data strobe signal, and an operation method thereof. The semiconductor memory device includes a...
US20090296501 Method and Apparatus for Implementing Write Levelization in Memory Subsystems  
Methods and apparatus for aligning a clock signal and a set of strobe signals are disclosed. In one embodiment, a memory controller includes a clock generator configured to generate the clock...
US20100054055 DATA INPUT/OUTPUT CIRCUIT  
A data input/output circuit includes an output unit for outputting a first data strobe signal and first data in response to an internal clock generated in a delay locked loop, a first transmission...
US20090190410 USING DIFFERENTIAL DATA STROBES IN NON-DIFFERENTIAL MODE TO ENHANCE DATA CAPTURE WINDOW  
A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether...
US20120257466 DUTY CYCLE DISTORTION CORRECTION  
Correction of duty cycle distortion of DQ and DQS signals between a memory controller and a memory is corrected by determining a duty cycle correction factor. The duty cycle distortion is corrected...
US20090316502 SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF  
There is provided a semiconductor memory device including: a source strobe signal generating unit configured to generate a source strobe signal having a first or a second activation width...
US20090175090 Buffered DRAM  
A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a...
US20090303809 CIRCUIT AND METHOD FOR TERMINATING DATA LINE OF SEMICONDUCTOR INTEGRATED CIRCUIT  
A data line termination circuit in a semiconductor integrated circuit includes a data line, a control unit for generating a termination control signal activated during a time section that includes...
US20090052261 DATA STROBE BUFFER AND MEMORY SYSTEM INCLUDING THE SAME  
A data strobe buffer and a memory system including the data strobe buffer are provided. The data strobe buffer includes: a first input/output node; a first driver coupled to the first input/output...
US20080137453 DATA I/O CONTROL SIGNAL GENERATING CIRCUIT IN A SEMICONDUCTOR MEMORY APPARATUS  
A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay...
US20090097339 Integrated Circuit Memory Devices Having Internal Command Generators Therein that Support Extended Command Sets Using Independent and Dependent Commands  
Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal...
US20110078370 MEMORY LINK INITIALIZATION  
Link initialization techniques to decouple the read training from the write training. Read training may be accomplished in a robust manner before write training is performed. These techniques may...
US20100074035 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device and method to perform a read operation and a write operation effectively. The semiconductor memory device and method includes: performing a first operation for...
Matches 1 - 50 out of 354 1 2 3 4 5 6 7 8 >