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US20100002515 Programming And Selectively Erasing Non-Volatile Storage  
A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements...
US20100002513 Selective Erase Operation For Non-Volatile Storage  
A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control...
US20100002514 Correcting For Over Programming Non-Volatile Storage  
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
US20090296475 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE  
When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process...
US20120243337 P-/METAL FLOATING GATE NON-VOLATILE STORAGE ELEMENT  
Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate....
US20120206967 PROGRAMMING AND SELECTIVELY ERASING NON-VOLATILE STORAGE  
A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements...
US20110228609 CORRECTING FOR OVER PROGRAMMING NON-VOLATILE STORAGE  
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
US20100074008 SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES  
Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting...
US20090175089 Retention in NVM with top or bottom injection  
Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM,...
US20110242899 EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE-VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE  
An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify...
US20080056012 Method for prioritized erasure of flash memory  
A method for prioritized erasure of a non-volatile storage device, the method including the steps of: providing at least one flash unit of the storage device, wherein each flash unit has a...
US20140185382 ERASE FOR NON-VOLATILE STORAGE  
Techniques are disclosed herein for erasing non-volatile storage elements. A sequence of increasing erase voltages may be applied to a substrate. The select line may be floated and many of the...
US20070103989 Data processing device having flash ROM, and a flash ROM data erasing method  
A data processing device 1 has flash ROM having a plurality of sectors, and a CPU for erasing data stored in a predetermined area of the flash ROM. A plurality of erase areas is set in the flash...
US20130279267 METHODS AND SYSTEMS FOR ERASE BIASING OF SPLIT-GATE NON-VOLATILE MEMORY CELLS  
Methods and systems are disclosed for erasing split-gate non-volatile memory (NVM) cells using select-gate erase voltages that are adjusted to reduce select-gate to control-gate break-down...
US20060198202 Flash memory backup system and method  
A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page...
US20090027970 Programming based on controller performance requirements  
Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels...
US20120113727 CONFIGURATION FINALIZATION ON FIRST VALID NAND COMMAND  
A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the...
US20100238730 CONTROLLING SELECT GATE VOLTAGE DURING ERASE TO IMPROVE ENDURANCE IN NON-VOLATILE MEMORY  
A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase...
US20130163336 Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory  
An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a...
US20090310422 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE  
A controller repeats an erase operation, an erase verify operation, and a step-up operation. A first storage unit stores a value of an erase start voltage applied first as an erase voltage when a...
US20100074016 DATA RETENTION OF LAST WORD LINE OF NON-VOLATILE MEMORY ARRAYS  
Techniques are disclosed herein for operating non-volatile storage. The techniques compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on...
US20100074006 DYNAMIC ERASE STATE IN FLASH DEVICE  
Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of...
US20070230253 Non-volatile semiconductor memory with page erase  
In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage...
US20090204747 Non binary flash array architecture and method of operation  
A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a...
US20100002524 FLOTOX-TYPE EEPROM  
In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type...
US20110235437 Single-Polycrystalline Silicon Electrically Erasable and Programmable Memory Device of Varied Gate Oxide Thickness, Using PIP or MIM Coupling Capacitor for Cell Size Reduction and Simultaneous VPP and VNN for Write Voltage Reduction  
A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal...
US20100238728 Method and apparatus of operating a non-volatile DRAM  
A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by positively charging the cell capacitor. A cell capacitor of an...
US20150117117 MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CONTROL GATES  
The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal...
US20090201741 Non-volatile memory cell with injector  
In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the...
US20090161440 INTEGRATED CIRCUITS AND DISCHARGE CIRCUITS  
An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the...
US20100172184 Asymmetric Single Poly NMOS Non-Volatile Memory Cell  
An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes...
US20100074007 FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL  
Flash memory systems and methods are provided for facilitating a single logical cell erasure in a flash memory device. Logical cell mapping is changed from using a single physical cell to using...
US20100020614 Non-Volatile Memory With Linear Estimation of Initial Programming Voltage  
In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is...
US20130121085 Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate  
A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the...
US20140269102 EEPROM MEMORY CELL WITH LOW VOLTAGE READ PATH AND HIGH VOLTAGE ERASE/WRITE PATH  
An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate...
US20090154254 CLUSTER BASED NON-VOLATILE MEMORY TRANSLATION LAYER  
An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks/sectors to...
US20100322006 NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME  
A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate...
US20080212376 METHODS OF OPERATING AND MANUFACTURING LOGIC DEVICE AND SEMICONDUCTOR DEVICE INCLUDING COMPLEMENTARY NONVOLATILE MEMORY DEVICE, AND READING CIRCUIT FOR THE SAME  
Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the...
US20070247910 NAND erase block size trimming apparatus and method  
A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure, the string subdivided by a plurality of separator elements placed in series with the memory cells...
US20130279268 EEPROM CELL WITH STORAGE CAPACITOR  
In an EEPROM cell, as a storage capacitor is added between a control plate and a tunneling plate, after the storage capacitor is charged for a time that is relatively smaller than a time necessary...
US20090175081 NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES  
A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors....
US20090213649 Semiconductor processing device and IC card  
A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22)...
US20150170748 Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current  
An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in...
US20120300551 NON-VOLATILE MEMORY CELL HEALING  
Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a...
US20090135659 ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE  
Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately...
US20100054043 Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing  
An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second...
US20140369136 SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES  
Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is...
US20060098492 Erase-verifying method of NAND type flash memory device and NAND type flash memory device thereof  
An erase-verifying method of a NAND type flash memory device and NAND type flash memory device thereof, wherein an erase-verifying operation is performed by applying a positive voltage as a source...
US20080219053 PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY  
A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable...
US20110013460 DYNAMICALLY ADJUSTABLE ERASE AND PROGRAM LEVELS FOR NON-VOLATILE MEMORY  
Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude,...