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US20120140567 NAND STEP UP VOLTAGE SWITCHING METHOD  
Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow...
US20140313825 DRAIN SELECT GATE VOLTAGE MANAGEMENT  
Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with...
US20110216600 DRAIN SELECT GATE VOLTAGE MANAGEMENT  
Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with...
US20130070530 HIGH ENDURANCE NON-VOLATILE STORAGE  
A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
US20130021849 Program Algorithm with Staircase Waveform Decomposed into Multiple Passes  
Programming algorithms suitable for non-volatile memory devices are presented, where the usual staircase type of waveform is decomposed into multiple passes. The same pulses are used, but their...
US20130329493 Natural Threshold Voltage Distribution Compaction In Non-Volatile Memory  
In a non-volatile memory system, a programming operation is performed in which faster-programming storage elements are distinguished from slower-programming storage elements. In one approach, the...
US20110267888 Controlling Select Gate Voltage During Erase To Improve Endurance In Non-Volatile Memory  
A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase...
US20120039125 Nonvolatile Memory with Correlated Multiple Pass Programming  
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are...
US20110019471 Nonvolatile Memory with Correlated Multiple Pass Programming  
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are...
US20100322005 REDUCED PROGRAMMING PULSE WIDTH FOR ENHANCED CHANNEL BOOSTING IN NON-VOLATILE STORAGE  
Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter...
US20070291623 CANTILEVER WITH CONTROL OF VERTICAL AND LATERAL POSITION OF CONTACT PROBE TIP  
An embodiment of a probe storage device in accordance with the present invention can include an electrostatic actuator for controlling the z-position of a cantilever having a contact probe tip...
US20110242899 EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE-VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE  
An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify...
US20100046301 INTELLIGENT CONTROL OF PROGRAM PULSE FOR NON-VOLATILE STORAGE  
To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses...
US20130223154 SEQUENTIAL PROGRAMMING OF SETS OF NON-VOLATILE ELEMENTS TO IMPROVE BOOST VOLTAGE CLAMPING  
A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an...
US20130308389 WORD LINE KICKING WHEN SENSING NON-VOLATILE STORAGE  
Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In...
US20120120729 WORD LINE KICKING WHEN SENSING NON-VOLATILE STORAGE  
Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In...
US20090086544 COMPENSATION OF NON-VOLATILE MEMORY CHIP NON-IDEALITIES BY PROGRAM PULSE ADJUSTMENT  
To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses...
US20120236654 PROGRAMMING NON-VOLATILE MEMORY WITH VARIABLE INITIAL PROGRAMMING PULSE  
Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage...
US20100238730 CONTROLLING SELECT GATE VOLTAGE DURING ERASE TO IMPROVE ENDURANCE IN NON-VOLATILE MEMORY  
A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase...
US20110249504 SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY  
In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial...
US20090067252 FUSE DATA ACQUISITION  
One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment includes detecting a signal...
US20100008145 METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE  
A method of programming nonvolatile memory devices. According to one programming method program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse...
US20100128529 NAND STEP VOLTAGE SWITCHING METHOD  
Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow...
US20120120726 VARIABLE INITIAL PROGRAM VOLTAGE MAGNITUDE FOR NON-VOLATILE STORAGE  
Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage...
US20150124531 IAS VOLTAGE GENERATOR FOR REFERENCE CELL AND BIAS VOLTAGE PROVIDING METHOD THEREFOR  
A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit....
US20150103601 MULTI-PASS SOFT PROGRAMMING  
Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft...
US20140269090 Periodic Erase Operation for a Non-Volatile Medium  
An apparatus, system, and method are disclosed for managing erase operations for a data storage medium. A method includes determining whether a use threshold for one or more non-volatile storage...
US20120275233 SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE  
Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage,...
US20090310421 Nonvolatile Memory with Correlated Multiple Pass Programming  
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are...
US20120039121 PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE  
Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the...
US20090201741 Non-volatile memory cell with injector  
In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the...
US20100329004 DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE  
A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine...
US20140043912 METHOD FOR KINK COMPENSATION IN A MEMORY  
This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential...
US20120307564 METHOD FOR KINK COMPENSATION IN A MEMORY  
This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential...
US20090213652 PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE  
Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a...
US20120250418 Natural Threshold Voltage Distribution Compaction In Non-Volatile Memory  
In a non-volatile memory system, a multi-phase programming operation is performed in which a drain-side select gate voltage (Vsgd) can be adjusted in different programming phases to accommodate...
US20150262675 Incremental step pulse programming (ISPP) scheme capable of determining a next starting pulse based on a current program-verify pulse for improving programming speed  
A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a current cell and executing a pre-program verify operation at a first program...
US20120033500 NATURAL THRESHOLD VOLTAGE DISTRIBUTION COMPACTION IN NON-VOLATILE MEMORY  
In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation...
US20120044768 PROGRAMMING TO MITIGATE MEMORY CELL PERFORMANCE DIFFERENCES  
Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum...
US20150023106 Adaptive Erase Recovery For Non-Volatile Memory (NVM) Systems  
Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery...
US20110019483 ADAPTIVE ERASE AND SOFT PROGRAMMING FOR MEMORY  
An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage...
US20080084761 HYBRID PROGRAMMING METHODS AND SYSTEMS FOR NON-VOLATILE MEMORY STORAGE ELEMENTS  
A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory...
US20110103150 NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING  
A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of...
US20110134701 MEMORY KINK COMPENSATION  
This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential...
US20130215680 AUTOMATIC SELECTIVE SLOW PROGRAM CONVERGENCE  
Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include...
US20110080789 AUTOMATIC SELECTIVE SLOW PROGRAM CONVERGENCE  
Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include...
US20120327712 METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS  
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory...
US20110188312 METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS  
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory...
US20090003075 FLASH MEMORY DEVICES AND PROGRAMMING METHODS THAT VARY PROGRAMMING CONDITIONS IN RESPONSE TO A SELECTED STEP INCREMENT  
A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected...
US20120188824 PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP  
A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine...