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US20120087187 Method for Programming a Floating Gate  
The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an...
US20130235658 METHOD FOR PROGRAMMING A FLOATING GATE  
The present invention provides circuits, systems, and methods for programming a floating gate. As described herein, a floating gate tunneling device is used with an analog comparison device in a...
US20080084747 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE  
A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile...
US20100002515 Programming And Selectively Erasing Non-Volatile Storage  
A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements...
US20140003155 SPLIT GATE PROGRAMMING  
A method for programming a split gate memory cell includes performing a first programming of the split gate memory cell in a first programming cycle of the split gate memory cell; and, subsequent...
US20130163340 NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE  
A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The...
US20090201734 Verified purge for flash storage device  
A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller...
US20100002513 Selective Erase Operation For Non-Volatile Storage  
A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control...
US20100002514 Correcting For Over Programming Non-Volatile Storage  
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
US20110292733 ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF  
A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed...
US20130107631 Method Of Programming A Split Gate Non-volatile Floating Gate Memory Cell Having A Separate Erase Gate  
A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of...
US20120106255 VOLTAGE GENERATION CIRCUIT WHICH IS CAPABLE OF REDUCING CIRCUIT AREA  
According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first...
US20120243337 P-/METAL FLOATING GATE NON-VOLATILE STORAGE ELEMENT  
Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate....
US20120106256 ELECTRONIC CIRCUIT WITH A FLOATING GATE TRANSISTOR AND A METHOD FOR DEACTIVATING A FLOATING GATE TRANSISTOR TEMPORARILY  
An electronic circuit includes a floating gate transistor with a floating gate capacitor. The floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating...
US20150236031 VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IMPLANT  
The present disclosure relates to a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of...
US20110235423 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE  
When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process...
US20150243361 EEPROM PROGRAMMING  
A method of programming an EEPROM, including: a first mode where a writing into cells is performed under a first voltage; and a second mode where the writing is performed under a second voltage...
US20120230111 LEVEL SHIFTING CIRCUIT  
A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a...
US20130223152 CLOCK GENERATOR  
A clock generator or oscillating circuit is provided to generate a clock signal with high Power Supply Rejection Ratio (PSSR), or a stable clock signal that is resistant to variations in the power...
US20150243363 ADJUSTING LOG LIKELIHOOD RATIO VALUES TO COMPENSATE MISPLACEMENT OF READ VOLTAGES  
An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the...
US20110007569 CORRECTING FOR OVER PROGRAMMING NON-VOLATILE STORAGE  
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
US20130070530 HIGH ENDURANCE NON-VOLATILE STORAGE  
A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
US20100074008 SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES  
Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting...
US20120127799 WRITE-PRECOMPENSATION AND VARIABLE WRITE BACKOFF  
A technique for writing data is disclosed. The technique includes estimating an amount of additional voltage on a victim cell of a solid-state storage device caused by writing to one or more other...
US20090175089 Retention in NVM with top or bottom injection  
Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM,...
US20090201732 System and method for purging a flash storage device  
A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and...
US20080304317 SOLID STATE MEMORY UTILIZING ANALOG COMMUNICATION OF DATA VALUES  
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices...
US20150200590 VOLTAGE GENERATOR CIRCUIT  
Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first transistor, a high-voltage switch circuit, and...
US20140029351 METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS FOR PROGRAM/ERASE OPERATIONS TO REDUCE PERFORMANCE DEGRADATION  
Methods and systems are disclosed for adjusting program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments...
US20130242664 INTERFACE CIRCUIT  
According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit...
US20130336066 SENSE AMPLIFIER CIRCUIT  
A sense amplifier (100) includes first and second inverters (112 and 113). The first inverter has an input terminal (116) and an OUT_B output node and a first transistor (124). The second inverter...
US20110242893 NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY  
A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series...
US20090237999 Different Combinations of Wordline Order and Look-Ahead Read to Improve Non-Volatile Memory Performance  
For a non-volatile memory storing three or more bits per cell, pages of data are written in an order where more than one, but less than all of the logical pages that a physical page along a...
US20150214964 Multi-Clock Generation Through Phase Locked Loop (PLL) Reference  
A circuit for providing a plurality of clock signals of differing frequencies includes: a phase locked loop section including a first voltage controller oscillator, connected to receive a...
US20100034025 NON-VOLATILE SEMICONDUCTOR STORAGE SYSTEM  
There is provided a non-volatile memory having electrically rewritable non-volatile memory cells arranged therein. A controller controls operation at the non-volatile memory. The non-volatile...
US20150036437 FLASH MEMORY CELL WITH CAPACITIVE COUPLING BETWEEN A METAL FLOATING GATE AND A METAL CONTROL GATE  
An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control...
US20100080060 DETERMINING MEMORY PAGE STATUS  
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without...
US20090080260 Programmable CSONOS logic element  
A complementary SONOS-type (CSONOS) logic device is programmed and erased with a common voltage. The CSONOS device retains data integrity over extended read endurance cycles.
US20150221383 MULTIPLE-TIME PROGRAMMABLE MEMORY  
A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first...
US20120275225 Variable Resistance Switch Suitable for Supplying High Voltage to Drive Load  
A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage...
US20130194874 Dynamic Healing Of Non-Volatile Memory Cells  
Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric...
US20080205145 MEMORY CONTROLLER CONTROLLING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR DEVICE  
A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit...
US20090027970 Programming based on controller performance requirements  
Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels...
US20120314502 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING  
A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process...
US20110286265 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING  
A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process...
US20130135936 MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE  
Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming...
US20110305090 MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE  
Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming...
US20110007566 MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE  
Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming...
US20120113727 CONFIGURATION FINALIZATION ON FIRST VALID NAND COMMAND  
A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the...
US20130028021 Simultaneous Sensing of Multiple Wordlines and Detection of NAND Failures  
Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these...