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US20100002515 Programming And Selectively Erasing Non-Volatile Storage  
A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements...
US20100002513 Selective Erase Operation For Non-Volatile Storage  
A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control...
US20100002514 Correcting For Over Programming Non-Volatile Storage  
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
US20090296475 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE  
When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process...
US20110235423 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE  
When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process...
US20140347933 NOR-BASED BCAM/TCAM CELL AND ARRAY WITH NAND SCALABILITY  
This invention discloses a 2T-string NOR-based CAM logic cell comprising two physical NAND cells connected in series with two horizontal WLs and one vertical BL and one vertical SL. Additionally,...
US20120206967 PROGRAMMING AND SELECTIVELY ERASING NON-VOLATILE STORAGE  
A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements...
US20110261621 PROGRAMMING AND SELECTIVELY ERASING NON-VOLATILE STORAGE  
A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements...
US20080123405 Implanted multi-bit NAND ROM  
The market for re-programmable Non-Volatile Memory is growing very fast with the storage of pictures, movies and games. The current NAND technology for mass storage is still limited by density...
US20140286101 BACK BIAS DURING PROGRAM VERIFY OF NON-VOLATILE STORAGE  
Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during...
US20120057407 CACHING SCHEME SYNERGY FOR EXTENT MIGRATION BETWEEN TIERS OF A STORAGE SYSTEM AND METHODS THEREOF  
A storage system according to one embodiment includes logic adapted for determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system, wherein a...
US20110228609 CORRECTING FOR OVER PROGRAMMING NON-VOLATILE STORAGE  
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
US20110007569 CORRECTING FOR OVER PROGRAMMING NON-VOLATILE STORAGE  
A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a...
US20130070530 HIGH ENDURANCE NON-VOLATILE STORAGE  
A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
US20150200019 ERASE SPEED ADJUSTMENT FOR ENDURANCE OF NON-VOLATILE STORAGE  
Techniques are disclosed herein for erasing non-volatile storage. The erase has two or more phases. The first phase includes erasing a group of non-volatile storage elements at a first speed until...
US20050041473 Non-volatile memory storage integrated circuit  
A non-volatile memory storage integrated circuit is disclosed. The non-volatile memory storage integrated circuit of the present invention comprises a controlling IC, a NAND IC and a memory IC....
US20130250690 SELECTED WORD LINE DEPENDENT SELECT GATE VOLTAGE DURING PROGRAM  
Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce...
US20130343129 EXTENDED SELECT GATE LIFETIME  
A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a...
US20110267888 Controlling Select Gate Voltage During Erase To Improve Endurance In Non-Volatile Memory  
A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase...
US20100322005 REDUCED PROGRAMMING PULSE WIDTH FOR ENHANCED CHANNEL BOOSTING IN NON-VOLATILE STORAGE  
Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter...
US20080089126 CIRCUITRY FOR RELIABILITY TESTING AS A FUNCTION OF SLEW  
A reliability test chain includes: a stress chain; and transition time control circuits coupled to tap points along the stress chain such that transition times of a signal on the stress chain are...
US20080316827 NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS  
A non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between...
US20090251967 NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL  
A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact...
US20100077134 FLASH DEVICE AND METHOD FOR IMPROVING PERFORMANCE OF FLASH DEVICE  
The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated...
US20100259989 OFFSET NON-VOLATILE STORAGE  
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce...
US20100259988 OFFSET NON-VOLATILE STORAGE  
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce...
US20140185382 ERASE FOR NON-VOLATILE STORAGE  
Techniques are disclosed herein for erasing non-volatile storage elements. A sequence of increasing erase voltages may be applied to a substrate. The select line may be floated and many of the...
US20150085579 CONTACT STRUCTURE AND FORMING METHOD  
Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second...
US20120275225 Variable Resistance Switch Suitable for Supplying High Voltage to Drive Load  
A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage...
US20140293701 Adjusting Control Gate Overdrive Of Select Gate Transistors During Programming Of Non-Volatile Memory  
In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive...
US20090303794 Structure and Method of A Field-Enhanced Charge Trapping-DRAM  
A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments,...
US20120176841 Flexible 2T-Based Fuzzy and Certain Matching Arrays  
A novel NVM-based 2T or 2nT NAND-cell for a NAND-array for PLD, PAL and matching functions is disclosed. The preferable NVM cell can be ROM or Flash. The 2T flash cell preferably uses FN for both...
US20130028021 Simultaneous Sensing of Multiple Wordlines and Detection of NAND Failures  
Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these...
US20100238730 CONTROLLING SELECT GATE VOLTAGE DURING ERASE TO IMPROVE ENDURANCE IN NON-VOLATILE MEMORY  
A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase...
US20130107627 BACK-BIASING WORD LINE SWITCH TRANSISTORS  
Back biasing word line switch transistors is disclosed. One embodiment includes word line switch transistors that are in a well in a substrate. A memory array having non-volatile storage devices...
US20130163336 Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory  
An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a...
US20090168534 THREE-DIMENSIONAL MEMORY DEVICE WITH MULTI-PLANE ARCHITECTURE  
Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats...
US20140307508 U-Shaped Common-Body Type Cell String  
A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one...
US20080137421 PATTERN LAYOUT OF INTEGRATED CIRCUIT  
In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with...
US20110267887 Reducing Energy Consumption When Applying Body Bias To Substrate Having Sets Of Nand Strings  
Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code...
US20150255166 Compensating Source Side Resistance Versus Word Line  
A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected...
US20090003060 High density NOR flash array architecture  
In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and...
US20140160848 SELECT GATE BIAS DURING PROGRAM OF NON-VOLATILE STORAGE  
Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND...
US20140254265 Flash Memory Cells, NAND Cell Units, Methods of Forming NAND Cell Units, and Methods of Programming NAND Cell Unit Strings  
Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate...
US20100074016 DATA RETENTION OF LAST WORD LINE OF NON-VOLATILE MEMORY ARRAYS  
Techniques are disclosed herein for operating non-volatile storage. The techniques compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on...
US20130250689 SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMMING  
Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a...
US20100061151 MULTI-PASS PROGRAMMING FOR MEMORY WITH REDUCED DATA STORAGE REQUIREMENT  
Coupling effects between adjacent floating gates in a non-volatile storage device are reduced in a multi-pass programming operation, while reducing program data storage requirements. In one...
US20130250688 SELECTED WORD LINE DEPENDENT PROGRAMMING VOLTAGE  
Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line...
US20090034333 Method for Managing a Non-Volatile Memory In a Smart Card  
The invention concerns a method for managing access to a non-volatile memory (VNVM), characterized in that said non-volatile memory (VNVM) results from the association of a non-volatile memory of...
US20150109864 INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING AND OPERATING THE SAME  
An integrated circuit and methods for manufacturing and operating the same are provided. The integrated circuit comprises a fork architecture and a first conductive structure. The fork...